Writing the Run In Standby bit (RUNSTDBY)
in the Control A register (CCL.CTRLA) to ‘1’ will allow the system
clock to be enabled in Standby Sleep mode.
If RUNSTDBY is ‘0’ the
system clock will be disabled in Standby Sleep mode. If the filter, edge detector,
and/or sequencer are enabled, the LUT output will be forced to ‘0’ in
Standby Sleep mode. In Idle Sleep mode, the TRUTH table decoder will continue the
operation and the LUT output will be refreshed accordingly, regardless of the RUNSTDBY
bit.
If the Clock Source bit (CLKSRC) in the LUT n Control A register
(CCL.LUTnCTRLA) is written to ‘1’, the LUT Input 2 (IN[2]) will always
clock the filter, edge detector, and sequencer. The availability of the IN[2] clock in
sleep modes will depend on the sleep settings of the peripheral used.