In order to ensure correct timing for half duplex UART operation, the UPDI has a built-in Guard Time mechanism to relax the timing when changing direction from RX mode to TX mode. The Guard Time is a number of IDLE bits inserted before the next Start bit is transmitted. The number of IDLE bits can be configured through the Guard Time Value (GTVAL) bit in the UPDI.CTRLA register. The duration of each IDLE bit is given by the baud rate used by the current transmission.
Do not set CTRLA.GTVAL to 0x7 without IDLE bits.
The UPDI Guard Time is the minimum IDLE time (see CTRLA.GTVAL) that the connected debugger will experience when waiting for data from the UPDI. The Maximum is the same as timeout (for example, 65536 UPDI clock cycles). The IDLE time before a transmission will be more than the expected Guard Time when the synchronization time plus the data bus accessing time is longer than the Guard Time. For example, the system is running on a slow clock.