Control C - Master SPI Mode

This register description is valid only when the USART is in Master SPI mode (CMODE written to MSPI). For other CMODE values, see CTRLC - Asynchronous mode.

See USART in Master SPI Mode for a full description of the Master SPI mode operation.

Name:
CTRLC
Offset:
0x07
Reset:
0x00
Access:
-
Bit76543210
CMODE[1:0]UDORDUCPHA
AccessR/WR/WR/WR/W
Reset0000

Bits 7:6 – CMODE[1:0]: USART Communication Mode

USART Communication Mode

Writing these bits select the communication mode of the USART.

Writing a value different than 0x03 to these bits alters the available bit fields in this register, see CTRLC - Asynchronous mode.

ValueNameDescription
0x00 ASYNCHRONOUS Asynchronous USART
0x01 SYNCHRONOUS Synchronous USART
0x02 IRCOM Infrared Communication
0x03 MSPI Master SPI

Bit 2 – UDORD: USART Data Order

USART Data Order

Writing this bit selects the frame format.

The receiver and transmitter use the same setting. Changing the setting of the UDORD bit will corrupt all ongoing communication for both the receiver and the transmitter.

ValueDescription
0 MSb of the data word is transmitted first
1 LSb of the data word is transmitted first

Bit 1 – UCPHA: USART Clock Phase

USART Clock Phase

The UCPHA bit setting determines if data are sampled on the leading (first) edge or tailing (last) edge of XCKn. Refer to Clock Generation for details.