Internal Reference Characteristics

Operating conditions:
Table 1. Power Supply, Reference, and Input Range
Symbol Description Conditions Min. Typ. Max. Unit
VDD Supply voltage CLKADC ≤ 1.5 MHz 1.8 - 5.5 V
CLKADC > 1.5 MHz 2.7 - 5.5
VREF Reference voltage REFSEL = Internal reference 0.55 - VDD-0.5 V
REFSEL = External reference 1.1   VDD
REFSEL = VDD 1.8 - 5.5
CIN Input capacitance SAMPCAP = 5 pF - 5 - pF
SAMPCAP = 10 pF - 10 -
VIN Input voltage range 0 - VREF V
IBAND Input bandwidth 1.1V ≤ VREF - - 57.5 kHz
Table 2. Clock and Timing Characteristics(1)
Symbol Description Conditions Min. Typ. Max. Unit
fADC Sample rate 1.1V ≤ VREF 15 - 115 ksps
1.1V ≤ VREF (8-bit resolution) 15 - 150
VREF = 0.55V (10 bits) 7.5 - 20
CLKADC Clock frequency VREF = 0.55V (10 bits) 100 - 260 kHz
1.1V ≤ VREF (10 bits) 200 - 1500
1.1V ≤ VREF (8-bit resolution) 200 - 2000
Ts Sampling time 2 2 33 CLKADC cycles
TCONV Conversion time (latency) Sampling time = 2 CLKADC 8.7 - 50 µs
TSTART Start-up time Internal VREF - 22 - µs
Note:
  1. 1.These parameters are for design guidance only and are not production tested.
Table 3. Accuracy Characteristics Internal Reference(2)
Symbol Description Conditions Min. Typ. Max. Unit
Res Resolution   - 10 - bit
INL Integral Non-linearity REFSEL = INTERNAL

VREF = 0.55V		 fADC = 7.7 ksps - 1.0 3.0 LSB
REFSEL = INTERNAL or VDD fADC = 15 ksps - 1.0 3.0
REFSEL = INTERNAL or VDD

1.1V ≤ VREF		 fADC = 77 ksps - 1.0 3.0
fADC = 115 ksps - 1.2 3.0
DNL(1) Differential Non-linearity REFSEL = INTERNAL

VREF = 0.55V		 fADC = 7.7 ksps - 0.6 1.3 LSB
REFSEL = INTERNAL

VREF = 1.1V		 fADC = 15 ksps - 0.4 1.2
REFSEL = INTERNAL or VDD

1.5V ≤ VREF		 fADC = 15 ksps - 0.4 1.0
REFSEL = INTERNAL or VDD

1.1V ≤ VREF		 fADC = 77 ksps - 0.4 1.0
REFSEL = INTERNAL

1.1V ≤ VREF		 fADC = 115 ksps - 0.5 1.6
REFSEL = VDD

1.8V ≤ VREF		 fADC = 115 ksps - 0.9 2.0
EABS Absolute accuracy REFSEL = INTERNAL

VREF = 1.1V		 T = [0-105]°C

VDD = [1.8V-3.6V]		 - <10 30 LSB
VDD = [1.8V-3.6V] - <15 40
REFSEL = VDD   - 2.5 5
REFSEL = INTERNAL   - <35 65
EGAIN Gain error REFSEL = INTERNAL

VREF = 1.1V		 T = [0-105]°C

VDD = [1.8V-3.6V]		 -25 ±15 25 LSB
VDD = [1.8V-3.6V] -35 ±20 35
REFSEL = VDD   -1 2 4
REFSEL = INTERNAL   -60 ±35 60
EOFF Offset error REFSEL = INTERNAL

VREF = 0.55V		   -5 -1 2 LSB
REFSEL = INTERNAL

1.1V ≤ VREF		   -4 -0.5 2 LSB
Note:
  1. 1.A DNL error of less than or equal to 1 LSB ensures a monotonic transfer function with no missing codes.
  2. 2.These parameters are for design guidance only and are not production tested.
  3. 3.Reference setting and fADC must fulfill the specification in “Clock and Timing Characteristics” and “Power Supply, Reference, and Input Range” tables.
Parent topic: ADC