Interrupt Flag Register - Split Mode
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LCMP2 | LCMP1 | LCMP0 | HUNF | LUNF | |||
| Access | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 |
Low byte Compare Channel 0 Interrupt Flag
See LCMP0 flag description.
Low byte Compare Channel 0 Interrupt Flag
See LCMP0 flag description.
Low byte Compare Channel 0 Interrupt Flag
The Low byte Compare Interrupt flag (LCMPn) is set on a compare match on the corresponding compare channel in the low byte timer.
For all modes of operation, the LCMPn flag will be set when a compare
match occurs between the Low Byte Timer Counter register (TCAn.LCNT) and the
corresponding compare register (TCAn.LCMPn). The LCMPn flag will not be cleared
automatically and has to be cleared by software. This is done by writing a
‘1’ to its bit location.
High byte Underflow Interrupt Flag
This flag is set on a high byte timer BOTTOM (underflow) condition.
HUNF is not automatically cleared and needs to be cleared by software. This is
done by writing a ‘1’ to its bit location.
Low byte Underflow Interrupt Flag
This flag is set on a low byte timer BOTTOM (underflow) condition.
LUNF is not automatically cleared and needs to be cleared by software. This is
done by writing a ‘1’ to its bit location.