TWI

Figure 1. TWI - Timing Requirements

Table 1. TWI - Specifications⁽¹⁾
Symbol	Description	Condition		Min.	Typ.	Max.	Unit
f_SCL	SCL clock frequency	Max. frequency requires system clock at 10 MHz, which, in turn, requires V_DD = [2.7, 5.5]V and T = [-40, 105]°C		0	-	1000	kHz
V_IH	Input high voltage			0.7×V_DD	-	-	V
V_IL	Input low voltage			-	-	0.3×V_DD	V
V_HYS	Hysteresis of Schmitt Trigger inputs			0.1×V_DD		0.4×V_DD	V
V_OL	Output low voltage	I_load = 20 mA, Fast mode+		-	-	0.2xV_DD	V
		I_load = 3 mA, Normal mode, V_DD > 2V		-	-	0.4V
		I_load = 3 mA, Normal mode, V_DD ≤ 2V		-	-	0.2×V_DD
I_OL	Low-level output current	f_SCL ≤ 400 kHz, V_OL = 0.4V		3	-	-	mA
I_OL	Low-level output current	f_SCL ≤ 1 MHz, V_OL = 0.4V		20	-	-	mA
C_B	Capacitive load for each bus line	f_SCL ≤ 100 kHz		-	-	400	pF
		f_SCL ≤ 400 kHz		-	-	400
		f_SCL ≤ 1 MHz		-	-	550
t_R	Rise time for both SDA and SCL	f_SCL ≤ 100 kHz		-	-	1000	ns
		f_SCL ≤ 400 kHz		20	-	300
		f_SCL ≤ 1 MHz		-	-	120
t_OF	Output fall time from V_IHmin to V_ILmax	10 pF < capacitance of bus line < 400 pF	f_SCL ≤ 100 kHz		-	250	ns
			f_SCL ≤ 400 kHz	20×(V_DD/5.5V)	-	250
			f_SCL ≤ 1 MHz	20×(V_DD/5.5V)	-	120
t_SP	Spikes suppressed by the input filter			0	-	50	ns
I_L	Input current for each I/O pin	0.1×V_DD < V_I < 0.9×V_DD		-	-	1	µA
C_I	Capacitance for each I/O pin			-	-	10	pF
R_P	Value of pull-up resistor	f_SCL ≤ 100 kHz		(V_DD-V_OL(max)) /I_OL	-	1000 ns/(0.8473×C_B)	Ω
		f_SCL ≤ 400 kHz		-	-	300 ns/(0.8473×C_B)
		f_SCL ≤ 1 MHz		-	-	120 ns/(0.8473×C_B)
t_HD;STA	Hold time (repeated) Start condition	f_SCL ≤ 100 kHz		4.0	-	-	µs
		f_SCL ≤ 400 kHz		0.6	-	-
		f_SCL ≤ 1 MHz		0.26	-	-
t_LOW	Low period of SCL Clock	f_SCL ≤ 100 kHz		4.7	-	-	µs
		f_SCL ≤ 400 kHz		1.3	-	-
		f_SCL ≤ 1 MHz		0.5	-	-
t_HIGH	High period of SCL Clock	f_SCL ≤ 100 kHz		4.0	-	-	µs
		f_SCL ≤ 400 kHz		0.6	-	-
		f_SCL ≤ 1 MHz		0.26	-	-
t_SU;STA	Setup time for a repeated Start condition	f_SCL ≤ 100 kHz		4.7	-	-	µs
		f_SCL ≤ 400 kHz		0.6	-	-
		f_SCL ≤ 1 MHz		0.26	-	-
t_HD;DAT	Data hold time	f_SCL ≤ 100 kHz		0	-	3.45	µs
		f_SCL ≤ 400 kHz		0	-	0.9
		f_SCL ≤ 1 MHz		0	-	0.45
t_SU;DAT	Data setup time	f_SCL ≤ 100 kHz		250	-	-	ns
		f_SCL ≤ 400 kHz		100	-	-
		f_SCL ≤ 1 MHz		50	-	-
t_SU;STO	Setup time for Stop condition	f_SCL ≤ 100 kHz		4	-	-	µs
		f_SCL ≤ 400 kHz		0.6	-	-
		f_SCL ≤ 1 MHz		0.26	-	-
t_BUF	Bus free time between a Stop and Start condition	f_SCL ≤ 100 kHz		4.7	-	-	µs
		f_SCL ≤ 400 kHz		1.3	-	-
		f_SCL ≤ 1 MHz		0.5	-	-

Note:

1.These parameters are for design guidance only and are not production tested.