The I/O pins of the device are controlled by instances of the PORT peripheral registers. Each PORT instance has up to eight I/O pins. The PORTs are named PORTA, PORTB, PORTC, etc. Refer to the “I/O Multiplexing and Considerations” chapter in the device Data Sheet to see which pins are controlled by what instance of PORT. The offsets of the PORT instances and of the corresponding Virtual PORT instances are listed in the “Peripherals and Architecture” section.
Each of the port pins has a corresponding bit in the Data Direction (PORTx.DIR) and Data Output Value (PORTx.OUT) registers to enable that pin as an output and to define the output state. For example, pin PA3 is controlled by DIR[3] and OUT[3] of the PORTA instance.
The input value of a PORT pin is synchronized to the main clock and then made accessible as the data input value (PORTx.IN). To reduce power consumption, these input synchronizers are not clocked if the Input Sense Configuration bit field (ISC) in PORTx.PINnCTRL is INPUT_DISABLE. The value of the pin can always be read, whether the pin is configured as input or output.
The PORT also supports synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, including the modes where no clocks are running.
All pin functions are configurable individually per pin. The pins have hardware read-modify-write (RMW) functionality for a safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin.
The PORT pin configuration also controls input and output selection of other device functions.