Full Range Duty Cycle Not Supported When Validating LIN Sync Field

For the LIN sync field, the USART is validating each bit to be within ±15% instead of the time between falling edges as described in the LIN specification. This allows a minimum duty cycle of 43.5% and a maximum duty cycle of 57.5%.

Work around

None.

Affected Silicon Revisions

ATtiny1616
Rev. A            
X            
ATtiny3216
Rev. A Rev. B Rev. C          
* * -          
Parent topic: USART - Universal Synchronous and Asynchronous Receiver and Transmitter