Master Mode Transmission

The following section describes the sequence of events when using the I²C in Master mode transmission.

1. 1.Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods is used to begin communication.

   When ABD is clear, the address buffers are enabled. In 7-bit Addressing mode, the 7-bit slave address is loaded into the I2CxADB1 register with the R/W bit clear. In 10-bit Addressing mode, the high address byte is loaded into the I2CxADB1 register with the R/W bit clear, and the low address byte is loaded into the I2CxADB0 register. The number of data bytes to be transmitted in one packet is loaded into the I2CxCNT register, and the first byte of data is loaded into the I2CxTXB transmit register. After these registers are loaded, master software must set the Start bit to begin communication. Master hardware must wait for BFRE to be set before transmitting the Start condition to avoid bus collisions.

   When ABD is set, the address buffers are disabled. In this case, the number of data bytes to be transmitted in one packet must be loaded into the I2CxCNT register before loading the transmit buffer. In 7-bit Addressing mode, the slave address is loaded into I2CxTXB with the R/W bit clear. Writing to the I2CxTXB register will automatically issue a Start condition via module hardware once the BFRE is set. In 10-bit Addressing mode, the slave’s high address byte with the R/W bit clear is loaded into the I2CxTXB register. Once the BFRE bit is set, module hardware shifts out the high address byte. In both 7-bit and 10-bit Addressing modes, when ABD is set, writes to the Start bit are ignored.

2. 2.Master hardware waits for the BFRE bit to be set, then shifts out the Start condition. Module hardware sets the Master Mode Active (MMA) and Start Condition Interrupt Flag (SCIF) bits.
3. 3.Master transmits either the 7-bit slave address with R/W clear or the 10-bit high address byte with R/W clear.

   In 7-bit mode, if the transmit buffer is empty (TXBE = 1), the I2CxCNT register is not ‘0’, and the CSD bit is clear, the I2CxTXIF and MDR bits are set, and the clock will be stretched by master hardware, allowing master software to write new data into I2CxTXB. Once I2CxTXB has been written, master hardware releases SCL and waits for an ACK/NACK sequence to be shifted in from the slave.

   In 10-bit mode, module hardware waits for the ACK/NACK from the slave. If a NACK is received, module hardware immediately issues a Stop condition. If an ACK is received, module hardware shifts out the 10-bit address low byte. If TXBE is set, and I2CxCNT is not ‘0’, the I2CxTXIF and MDR bits are set, and SCL is stretched on the 8th falling SCL edge to allow the master to load new data into I2CxTXB. Once I2CxTXB has been written, master hardware releases SCL and waits for an ACK/NACK sequence to be shifted in from the slave.

4. 4.Master hardware clock out the 9th SCL pulse and waits for the ACK response from the slave. If the master receives a NACK, master hardware will issue a Stop condition.
5. 5.If the master receives an ACK, module hardware transfers the data byte currently in the transmit buffer into the transmit shift register, and the value of I2CxCNT is decremented by one.
6. 6.Master hardware checks to see if I2CxCNT is ‘0’.

   If I2CxCNT is not ‘0’, go back to step 5. If I2CxCNT is ‘0’, and ABD is clear,master hardware issues a Stop condition, or sets the MDR bit if the RSEN bit is set and waits for master software to set the Start bit again to issue a Restart condition.

   If I2CxCNT is ‘0’ and the ABD bit is set, hardware issues a Stop condition, or sets the MDR bit if the RSEN bit is also set and waits for software to load the I2CxTXB register with new address data.