Contents

Introduction Feature Description Configuration Summary Ordering Information Block Diagram Pin Configurations Pin Descriptions VCC GND Port A (PA[7:0]) Port B (PB[3:0]) RESET I/O Multiplexing General Information Resources Data Retention About Code Examples AVR CPU Core Overview Features Block Diagram ALU – Arithmetic Logic Unit Status Register General Purpose Register File The X-register, Y-register, and Z-register Stack Pointer Accessing 16-bit Registers Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time Register Description Configuration Change Protection Register Stack Pointer Register Low and High byte Status Register AVR Memories Overview Features In-System Reprogrammable Flash Program Memory SRAM Data Memory Data Memory Access Times I/O Memory Clock System Overview Clock Distribution Clock Subsystems CPU Clock – clkCPU I/O Clock – clkI/O NVM Clock – clkNVM ADC Clock – clkADC Clock Sources Calibrated Internal 8MHz Oscillator External Clock Internal 128kHz Oscillator Switching Clock Source Default Clock Source System Clock Prescaler Switching Prescaler Setting Starting Starting from Reset Starting from Power-Down Mode Starting from Idle / ADC Noise Reduction / Standby Mode Register Description Clock Main Settings Register Oscillator Calibration Register Clock Prescaler Register Power Management and Sleep Modes Overview Features Sleep Modes Idle Mode ADC Noise Reduction Mode Power-Down Mode Standby Mode Power Reduction Register Minimizing Power Consumption Analog Comparator Analog to Digital Converter Internal Voltage Reference Watchdog Timer Port Pins Register Description Sleep Mode Control Register Power Reduction Register SCRST - System Control and Reset Overview Features Resetting the AVR Reset Sources Power-on Reset VCC Level Monitoring External Reset Watchdog System Reset Watchdog Timer Overview Procedure for Changing the Watchdog Timer Configuration Safety Level 1 Safety Level 2 Code Examples Register Description Watchdog Timer Control Register VCC Level Monitoring Control and Status register Reset Flag Register Interrupts Overview Interrupt Vectors External Interrupts Low Level Interrupt Pin Change Interrupt Timing Register Description External Interrupt Control Register A External Interrupt Mask Register External Interrupt Flag Register Pin Change Interrupt Control Register Pin Change Interrupt Flag Register Pin Change Mask Register 0 Pin Change Mask Register 1 I/O-Ports Overview Features I/O Pin Equivalent Schematic Ports as General Digital I/O Configuring the Pin Toggling the Pin Break-Before-Make Switching Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected Pins Program Example Alternate Port Functions Alternate Functions of Port A Alternate Functions of Port B Register Description Port A Input Pins Address Port A Data Direction Register Port A Data Register Port A Pull-up Enable Control Register Port B Input Pins Address Port B Data Direction Register Port B Data Register Port B Pull-up Enable Control Register Port Control Register USART0 Overview Features Block Diagram Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2Xn) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bits Sending Frames with 9 Data Bit Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Start Frame Detection Multi-processor Communication Mode Using MPCMn Examples of Baud Rate Setting Register Description USART I/O Data Register 0 USART Control and Status Register 0 A USART Control and Status Register 0 B USART Control and Status Register 0 C USART Control and Status Register 0 D USART Baud Rate 0 Register Low and High byte USARTSPI - USART in SPI Mode Overview Features Clock Generation SPI Data Modes and Timing Frame Formats USART MSPIM Initialization Data Transfer Transmitter and Receiver Flags and Interrupts Disabling the Transmitter or Receiver AVR USART MSPIM vs. AVR SPI Register Description 16-bit Timer/Counter1 with PWM Overview Features Block Diagram Definitions Registers Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Internal Clock Source - Prescaler Prescaler Reset External Clock Source Counter Unit Input Capture Unit Input Capture Trigger Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams Register Description Timer/Counter0 Control Register A Timer/Counter0 Control Register B Timer/Counter0 Control Register C Timer/Counter 0 Low and High byte Output Comparte Register A 0 Low and High byte Output Comparte Register B 0 Low and High byte Input Capture Register 0 Low and High byte Timer/Counter0 Interrupt Mask Register Timer/Counter0 Interrupt Flag Register General Timer/Counter Control Register AC - Analog Comparator Overview Features Block Diagram Register Description Analog Comparator Control and Status Register Analog Comparator Control and Status Register 0 Digital Input Disable Register 0 ADC - Analog to Digital Converter Overview Features Block Diagram Operation Starting a Conversion Prescaling and Conversion Timing Changing Channel or Reference Selection ADC Input Channels ADC Voltage Reference ADC Noise Canceler Analog Input Circuitry Analog Noise Canceling Techniques ADC Accuracy Definitions ADC Conversion Result Single-Ended Conversion Register Description ADC Multiplexer Selection Register ADC Control and Status Register A ADC Control and Status Register B ADC Data Register Low and High Byte (ADLAR=0) ADC Data Register Low and High Byte (ADLAR=1) Digital Input Disable Register 0 MEMPROG- Memory Programming Overview Features Non-Volatile Memories (NVM) Non-Volatile Memory Lock Bits Flash Memory Configuration Section Latching of Configuration Bits Signature Section Signature Row Summary Device ID n Serial Number Byte n Calibration Section Accessing the NVM Addressing the Flash Reading the Flash Programming the Flash Chip Erase Erasing the Code Section Writing a Code Word Erasing the Configuration Section Writing a Configuration Word Reading NVM Lock Bits Writing NVM Lock Bits Self programming External Programming Entering External Programming Mode Exiting External Programming Mode Register Description Non-Volatile Memory Control and Status Register Non-Volatile Memory Command Register TPI-Tiny Programming Interface Overview Features Block Diagram Physical Layer of Tiny Programming Interface Enabling Disabling Frame Format Parity Bit Calculation Supported Characters Operation Serial Data Reception Serial Data Transmission Collision Detection Exception Direction Change Access Layer of Tiny Programming Interface Message format Exception Handling and Synchronisation Instruction Set SLD - Serial LoaD from data space using indirect addressing SST - Serial STore to data space using indirect addressing SSTPR - Serial STore to Pointer Register SIN - Serial IN from i/o space using direct addressing SOUT - Serial OUT to i/o space using direct addressing SLDCS - Serial LoaD data from Control and Status space using direct addressing SSTCS - Serial STore data to Control and Status space using direct addressing SKEY - Serial KEY signaling Accessing the Non-Volatile Memory Controller Control and Status Space Register Descriptions Tiny Programming Interface Identification Register Tiny Programming Interface Physical Layer Control Register Tiny Programming Interface Status Register Electrical Characteristics Absolute Maximum Ratings* DC Characteristics Speed Clock Characteristics Accuracy of Calibrated Internal Oscillator External Clock Drive System and Reset Characteristics Power-On Reset VCC Level Monitor Analog Comparator Characteristics ADC Characteristics Serial Programming Characteristics Typical Characteristics Active Supply Current Idle Supply Current Supply Current of I/O Modules Power-down Supply Current Pin Driver Strength Pin Threshold and Hysteresis Analog Comparator Offset Pin Pull-up Internal Oscillator Speed VLM Thresholds Current Consumption of Peripheral Units Current Consumption in Reset and Reset Pulsewidth Register Summary Note Instruction Set Summary Packaging Information 8-pin UDFN 8-pin SOIC150 14-pin SOIC150 Errata ATtiny102 Rev.A ATtiny104 Rev.A Datasheet Revision History Rev D - 10/2016 Rev C - 07/2016 Rev B - 06/2016 Rev A - 02/2016 Legal Disclaimer