The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
- TID 40001583 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
- TID 120000272 - Embedded Hosts > Full Speed
Electrical configuration required to be USB compliance:
- The CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode)
- The operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
- The GCLK_USB frequency accuracy source must be less than:
- In USB device mode, 48MHz +/-0.25%
- In USB host mode, 48MHz +/-0.05%
| Clock setup | USB Device | USB Host | ||
|---|---|---|---|---|
| DFLL48M | Open loop | No | No | |
| Closed loop, any internal OSC source | No | No | ||
| Closed loop, any external XOSC source | Yes | No | ||
| Closed loop, USB SOF source (USB recovery mode)(1) | Yes(2) | N/A | ||
| FDPLL96M | Any internal OSC source (32K, 8M, ... ) | No | No | |
| Any external XOSC source (< 1MHz) | Yes | No | ||
| Any external XOSC source (> 1MHz) | Yes(3) | Yes | ||
Notes: 1. When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a USB clock at +/-0.25% before 11ms after a resume.
2. Very high signal quality and crystal less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up time (See TDRSMDN in USB specification).