Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics

Table 1. FDPLL96M Characteristics⁽¹⁾ (Device Variant A)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_IN	Input frequency		32	-	2000	KHz
f_OUT	Output frequency		48	-	96	MHz
I_FDPLL96M	Current consumption	f_IN= 32 kHz, f_OUT= 48 MHz		500	700	μA
I_FDPLL96M	Current consumption	f_IN= 32 kHz, f_OUT= 96 MHz		900	1200	μA
J_p	Period jitter	f_IN= 32 kHz, f_OUT= 48 MHz	-	1.5	2.0	%
		f_IN= 32 kHz, f_OUT= 96 MHz		3.0	10.0
		f_IN= 2 MHz, f_OUT= 48 MHz		1.3	2.0
		f_IN= 2 MHz, f_OUT= 96 MHz		3.0	7.0
t_LOCK	Lock Time	After start-up, time to get lock signal. f_IN= 32 kHz, f_OUT= 96 MHz		1.3	2	ms
t_LOCK	Lock Time	f_IN= 2 MHz, f_OUT= 96 MHz		25	50	μs
Duty	Duty cycle		40	50	60	%

Table 2. FDPLL96M Characteristics⁽¹⁾ (Device Variant B)
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_IN	Input frequency		32	-	2000	KHz
f_OUT	Output frequency		48	-	96	MHz
I_FDPLL96M	Current consumption	f_IN= 32 kHz, f_OUT= 48 MHz		500	700	μA
I_FDPLL96M	Current consumption	f_IN= 32 kHz, f_OUT= 96 MHz		900	1200	μA
J_p	Period jitter	f_IN= 32 kHz, f_OUT= 48 MHz	-	1.5	2.1	%
		f_IN= 32 kHz, f_OUT= 96 MHz		4.0	10.0
		f_IN= 2 MHz, f_OUT= 48 MHz		1.6	2.2
		f_IN= 2 MHz, f_OUT= 96 MHz		4.6	10.2
t_LOCK	Lock Time	After start-up, time to get lock signal. f_IN= 32 kHz, f_OUT= 96 MHz		1.2	2	ms
t_LOCK	Lock Time	f_IN= 2 MHz, f_OUT= 96 MHz		25	50	μs
Duty	Duty cycle		40	50	60	%

Note: