| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TXUR1 | TXUR0 | TXRDY1 | TXRDY0 | ||||
| Access | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | |||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RXOR1 | RXOR0 | RXRDY1 | RXRDY0 | ||||
| Access | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 |
Transmit Underrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transmit Underrun x Interrupt Enable bit, which disables the Transmit Underrun x interrupt.
| Value | Description |
|---|---|
| 0 | The Transmit Underrun x interrupt is disabled. |
| 1 | The Transmit Underrun x interrupt is enabled. |
Transmit Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Transmit Ready x Interrupt Enable bit, which disables the Transmit Ready x interrupt.
| Value | Description |
|---|---|
| 0 | The Transmit Ready x interrupt is disabled. |
| 1 | The Transmit Ready x interrupt is enabled. |
Receive Overrun x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Receive Overrun x Interrupt Enable bit, which disables the Receive Overrun x interrupt.
| Value | Description |
|---|---|
| 0 | The Receive Overrun x interrupt is disabled. |
| 1 | The Receive Overrun x interrupt is enabled. |
Receive Ready x Interrupt Enable [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Receive Ready x Interrupt Enable bit, which disables the Receive Ready x interrupt.
| Value | Description |
|---|---|
| 0 | The Receive Ready x interrupt is disabled. |
| 1 | The Receive Ready x interrupt is enabled. |