| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MCKOUTINV | SCKOUTINV | FSOUTINV | MCKOUTDIV[4:0] | ||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MCKDIV[4:0] | MCKEN | MCKSEL | |||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SCKSEL | FSINV | FSSEL | |||||
| Access | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | ||||
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BITDELAY | FSWIDTH[1:0] | NBSLOTS[2:0] | SLOTSIZE[1:0] | ||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Master Clock Output Invert
| Value | Description |
|---|---|
| 0 | The Master Clock n is output without inversion. |
| 1 | The Master Clock n is inverted before being output. |
Serial Clock Output Invert
| Value | Description |
|---|---|
| 0 | The Serial Clock n is output without inversion. |
| 1 | The Serial Clock n is inverted before being output. |
Frame Sync Output Invert
| Value | Description |
|---|---|
| 0 | The Frame Sync n is output without inversion. |
| 1 | The Frame Sync n is inverted before being output. |
Master Clock Output Division Factor
The generic clock selected by MCKSEL is divided by (MCKOUTDIV + 1) to obtain the Master Clock n output.
Master Clock Division Factor
The Master Clock n is divided by (MCKDIV + 1) to obtain the Serial Clock n.
Master Clock Enable
| Value | Description |
|---|---|
| 0 | The Master Clock n division and output is disabled. |
| 1 | The Master Clock n division and output is enabled. |
Master Clock Select
This field selects the source of the Master Clock n.
| MCKSEL | Name | Description |
|---|---|---|
| 0x0 | GCLK | GCLK_I2S_n is used as Master Clock n source |
| 0x1 | MCKPIN | MCKn input pin is used as Master Clock n source |
Serial Clock Select
This field selects the source of the Serial Clock n.
| SCKSEL | Name | Description |
|---|---|---|
| 0x0 | MCKDIV | Divided Master Clock n is used as Serial Clock n source |
| 0x1 | SCKPIN | SCKn input pin is used as Serial Clock n source |
Frame Sync Invert
| Value | Description |
|---|---|
| 0 | The Frame Sync n is used without inversion. |
| 1 | The Frame Sync n is inverted before being used. |
Frame Sync Select
This field selects the source of the Frame Sync n.
| FSSEL | Name | Description |
|---|---|---|
| 0x0 | SCKDIV | Divided Serial Clock n is used as Frame Sync n source |
| 0x1 | FSPIN | FSn input pin is used as Frame Sync n source |
Data Delay from Frame Sync
| BITDELAY | Name | Description |
|---|---|---|
| 0x0 | LJ | Left Justified (0 Bit Delay) |
| 0x1 | I2S | I2S (1 Bit Delay) |
Frame Sync Width
This field selects the duration of the Frame Sync output pulses.
When not in Burst mode, the Clock unit n operates in continuous mode when enabled, with periodic Frame Sync pulses and Data samples.
In Burst mode, a single Data transfer starts at each Frame Sync pulse; these pulses are 1-bit wide and occur only when a Data transfer is requested. Note that the compact stereo modes (16C and 8C) are not supported in the Burst mode.
| FSWIDTH[1:0] | Name | Description |
|---|---|---|
| 0x0 | SLOT | Frame Sync Pulse is 1 Slot wide (default for I2S protocol) |
| 0x1 | HALF | Frame Sync Pulse is half a Frame wide |
| 0x2 | BIT | Frame Sync Pulse is 1 Bit wide |
| 0x3 | BURST | Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested |
Number of Slots in Frame
Each Frame for Clock Unit n is composed of (NBSLOTS + 1) Slots.
Slot Size
Each Slot for Clock Unit n is composed of a number of bits specified by SLOTSIZE.
| SLOTSIZE[1:0] | Name | Description |
|---|---|---|
| 0x0 | 8 | 8-bit Slot for Clock Unit n |
| 0x1 | 16 | 16-bit Slot for Clock Unit n |
| 0x2 | 24 | 24-bit Slot for Clock Unit n |
| 0x3 | 32 | 32-bit Slot for Clock Unit n |