| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DIV | ENABLE | CLKRDY | LOCK | ||||
| Access | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 |
Divider Enable
| Value | Description |
|---|---|
| 0 | The reference clock divider is disabled. |
| 1 | The reference clock divider is enabled. |
DPLL Enable
| Value | Description |
|---|---|
| 0 | The DPLL is disabled. |
| 1 | The DPLL is enabled. |
Output Clock Ready
| Value | Description |
|---|---|
| 0 | The DPLL output clock is off |
| 1 | The DPLL output clock in on. |
DPLL Lock Status
| Value | Description |
|---|---|
| 0 | The DPLL Lock signal is cleared. |
| 1 | The DPLL Lock signal is asserted. |