| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PINT[15:8] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PINT[7:0] | |||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
The flag PINT[n] is set when an interrupt is triggered by the pipe n. See PINTFLAG register in the Host Pipe Register section.
This bit will be cleared when there are no interrupts pending for Pipe n.
Writing to this bit has no effect.