I2S Timing

Figure 1. I2S Timing Master Mode

Figure 2. I2S Timing Slave Mode

Figure 3. I2S Timing PDM2 Mode

Table 1. I2S Timing Characteristics and Requirements (Device Variant A)
Symbol	Description	Mode	VDD=1.8V			VDD=3.3V			Units
Symbol	Description	Mode	Min.	Typ.	Max.	Min.	Typ.	Max	Units
t_{M_MCKOR}	I2S MCK rise time⁽³⁾	Master mode / Capacitive load CL = 15 pF			10			4.7	ns
t_{M_MCKOF}	I2S MCK fall time⁽³⁾	Master mode / Capacitive load CL = 15 pF			12.1			5.3	ns
d_{M_MCKO}	I2S MCK duty cycle	Master mode	45.4		50	45.4		50	%
d_{M_MCKI}	I2S MCK duty cycle	Master mode, pin is input (1b)		50			50		%
t_{M_SCKOR}	I2S SCK rise time⁽²⁾	Master mode / Capacitive load CL = 15 pF			9.7			4.6	ns
t_{M_SCKOF}	I2S SCK fall time⁽³⁾	Master mode / Capacitive load CL = 15 pF			10.2			4.5	ns
d_{M_SCKO}	I2S SCK duty cycle	Master mode	45.6		50	45.6		50	%
f_{M_SCKO}, 1/t_{M_SCKO}	I2S SCK frequency	Master mode, Supposing external device response delay is 30ns			7.8			9.5	MHz
f_{S_SCKI}, 1/t_{S_SCKI}	I2S SCK frequency	Slave mode, Supposing external device response delay is 30ns			14.4			14.8	MHz
d_{S_SCKO}	I2S SCK duty cycle	Slave mode		50			50		%
t_{M_FSOV}	FS valid time	Master mode			4.1			4	ns
t_{M_FSOH}	FS hold time	Master mode	-0.9			-0.9			ns
t_{S_FSIS}	FS setup time	Slave mode	2.3			1.5			ns
t_{S_FSIH}	FS hold time	Slave mode	0			0			ns
t_{M_SDIS}	Data input setup time	Master mode	36.2			24.5			ns
t_{M_SDIH}	Data input hold time	Master mode	-8.2			-8.2			ns
t_{S_SDIS}	Data input setup time	Slave mode	4.8			3.9			ns
t_{S_SDIH}	Data input hold time	Slave mode	1.2			1.2			ns
t_{M_SDOV}	Data output valid time	Master transmitter			5.9			4.8	ns
t_{M_SDOH}	Data output hold time	Master transmitter	-0.5			-0.5			ns
t_{S_SDOV}	Data output valid time	Slave transmitter			37.8			25.9	ns
t_{S_SDOH}	Data output hold time	Slave transmitter	37.6			25.7			ns
t_PDM2LS	Data input setup time	Master mode PDM2 Left	36.2			24.5			ns
t_PDM2LH	Data input hold time	Master mode PDM2 Left	-8.2			-8.2			ns
t_PDM2RS	Data input setup time	Master mode PDM2 Right	31.9			20.9			ns
t_PDM2RH	Data input hold time	Master mode PDM2 Right	-6.7			-6.7			ns

All timing characteristics given for 15pF capacitive load.
These values are based on simulations and not covered by test limits in production.
See I/O Pin Characteristics.

Table 2. I2S Timing Characteristics and Requirements (Device Variant B)
Name	Description	Mode	VDD=1.8V			VDD=3.3V			Units
			Min.	Typ.	Max.	Min.	Typ.	Max.
t_{M_MCKOR}	I2S MCK rise time⁽³⁾	Master mode / Capacitive load CL = 15 pF			9.9			4.7	ns
t_{M_MCKOF}	I2S MCK fall time⁽³⁾	Master mode / Capacitive load CL = 15 pF			12.3			5.4	ns
d_{M_MCKO}	I2S MCK duty cycle	Master mode	46.9		50	47.3		50	%
d_{M_MCKI}	I2S MCK duty cycle	Master mode, pin is input (1b)		50			50		%
t_{M_SCKOR}	I2S SCK rise time⁽³⁾	Master mode / Capacitive load CL = 15 pF			9.7			4.6	ns
t_{M_SCKOF}	I2S SCK fall time⁽³⁾	Master mode / Capacitive load CL = 15 pF			10.3			4.6	ns
d_{M_SCKO}	I2S SCK duty cycle	Master mode	46.9		50	47.2		50	%
f_{M_SCKO}, 1/t_{M_SCKO}	I2S SCK frequency	Master mode, Supposing external device response delay is 30ns			7.7			9.2	MHz
f_{S_SCKI}, 1/t_{S_SCKI}	I2S SCK frequency	Slave mode, Supposing external device response delay is 30ns			12.7			13	MHz
d_{S_SCKO}	I2S SCK duty cycle	Slave mode		50			50		%
t_{M_FSOV}	FS valid time	Master mode			2.6			1.9	ns
t_{M_FSOH}	FS hold time	Master mode	-0.1			-0.1			ns
t_{S_FSIS}	FS setup time	Slave mode	6.2			5.3			ns
t_{S_FSIH}	FS hold time	Slave mode	0			0			ns
t_{M_SDIS}	Data input setup time	Master mode	37.4			25.9			ns
t_{M_SDIH}	Data input hold time	Master mode	-8.2			-8.2			ns
t_{S_SDIS}	Data input setup time	Slave mode	9.2			8.3			ns
t_{S_SDIH}	Data input hold time	Slave mode	3.8			3.7			ns
t_{M_SDOV}	Data output valid time	Master transmitter			2.7			1.9	ns
t_{M_SDOH}	Data output hold time	Master transmitter	-0.1			-0.1			ns
t_{S_SDOV}	Data output valid time	Slave transmitter			31.2			19.7	ns
t_{S_SDOH}	Data output hold time	Slave transmitter	30.6			18.9			ns
t_PDM2LS	Data input setup time	Master mode PDM2 Left	36.9			25.3			ns
t_PDM2LH	Data input hold time	Master mode PDM2 Left	-8.2			-8.2			ns
t_PDM2RS	Data input setup time	Master mode PDM2 Right	31.9			21.1			ns
t_PDM2RH	Data input hold time	Master mode PDM2 Right	-7			-7			ns

All timing characteristics given for 15pF capacitive load.
These values are based on simulations and not covered by test limits in production.
See I/O Pin Characteristics