Synchronization Busy
Name:
SYNCBUSY
Offset:
0x18
Reset:
0x0000
Access:
-
Bit15141312111098
DATA1 DATA0
AccessRR
Reset00
Bit76543210
SEREN1 SEREN0 CKEN1 CKEN0 ENABLESWRST
AccessRRRRRR
Reset000000

Bit 1 – ENABLE: Enable Synchronization Status

Enable Synchronization Status

This bit is cleared when the synchronization of CTRLA.ENABLE bit between the clock domains is complete.

This bit is set when the synchronization of CTRLA.ENABLE bit between the clock domains is started.

Bit 0 – SWRST: Software Reset Synchronization Status

Software Reset Synchronization Status

This bit is cleared when the synchronization of CTRLA.SWRST bit between the clock domains is complete.

This bit is set when the synchronization of CTRLA.SWRST bit between the clock domains is started.

Bits 8,9 – DATAx : Data x Synchronization Status [x=1..0]

Data x Synchronization Status [x=1..0]

Bit DATAx is cleared when the synchronization of DATA Holding register (DATAx) between the clock domains is complete.

Bit DATAx is set when the synchronization of DATA Holding register (DATAx) between the clock domains is started.

Bits 4,5 – SERENx : Serializer x Enable Synchronization Status [x=1..0]

Serializer x Enable Synchronization Status [x=1..0]

Bit SERENx is cleared when the synchronization of CTRLA.SERENx bit between the clock domains is complete.

Bit SERENx is set when the synchronization of CTRLA.SERENx bit between the clock domains is started.

Bits 2,3 – CKENx : Clock Unit x Enable Synchronization Status [x=1..0]

Clock Unit x Enable Synchronization Status [x=1..0]

Bit CKENx is cleared when the synchronization of CTRLA.CKENx bit between the clock domains is complete.

Bit CKENx is set when the synchronization of CTRLA.CKENx bit between the clock domains is started.