DPLL Control B
Name:
DPLLCTRLB
Offset:
0x4C
Reset:
0x00000000
Access:
Write-Protected
Bit3130292827262524
DIV[10:8]
AccessR/WR/WR/W
Reset000
Bit2322212019181716
DIV[7:0]
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit15141312111098
LBYPASSLTIME[2:0]
AccessR/WR/WR/WR/W
Reset0000
Bit76543210
REFCLK[1:0]WUFLPENFILTER[1:0]
AccessR/WR/WR/WR/WR/WR/W
Reset000000

Bits 26:16 – DIV[10:0]: Clock Divider

Clock Divider

These bits are used to set the XOSC clock source division factor. Refer to Principle of Operation.

Bit 12 – LBYPASS: Lock Bypass

Lock Bypass

ValueDescription
0 Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1 Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.

Bits 10:8 – LTIME[2:0]: Lock Time

Lock Time

These bits select Lock Timeout.

LTIME[2:0] Name Description
0x0 DEFAULT No time-out
0x1-0x3   Reserved
0x4 8MS Time-out if no lock within 8 ms
0x5 9MS Time-out if no lock within 9 ms
0x6 10MS Time-out if no lock within 10 ms
0x7 11MS Time-out if no lock within 11 ms

Bits 5:4 – REFCLK[1:0]: Reference Clock Selection

Reference Clock Selection

These bits select the CLK_FDPLL96M_REF source.

REFCLK[1:0] Name Description
0x0 XOSC32 XOSC32 clock reference
0x1 XOSC XOSC clock reference
0x2 GCLK_DPLL GCLK_DPLL clock reference
0x3   Reserved

Bit 3 – WUF: Wake Up Fast

Wake Up Fast

ValueDescription
0 DPLL CK output is gated until complete startup time and lock time.
1 DPLL CK output is gated until startup time only.

Bit 2 – LPEN: Low-Power Enable

Low-Power Enable

ValueDescription
0 The time to digital converter is selected.
1 The time to digital converter is not selected, this will improve power consumption but increase the output jitter.

Bits 1:0 – FILTER[1:0]: Proportional Integral Filter Selection

Proportional Integral Filter Selection

These bits select the DPLL filter type.

FILTER[1:0] Name Description
0x0 DEFAULT Default filter mode
0x1 LBFILT Low bandwidth filter
0x2 HBFILT High bandwidth filter
0x3 HDFILT High damping filter