Interrupt Enable Set
Name:
INTENSET
Offset:
0x14
Reset:
0x00000000
Access:
Write-Protected
Bit3130292827262524
EVD11 EVD10 EVD9 EVD8
AccessR/WR/WR/WR/W
Reset0000
Bit2322212019181716
OVR11OVR10OVR9OVR8
AccessR/WR/WR/WR/W
Reset0000
Bit15141312111098
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000
Bit76543210
OVR7OVR6OVR5OVR4OVR3OVR2OVR1OVR0
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bits 27,26,25,24,15,14,13,12,11,10,9,8 – EVDn : Channel n Event Detection Interrupt Enable [n=11..0]

Channel n Event Detection Interrupt Enable [n=11..0]

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Event Detected Channel n Interrupt Enable bit, which enables the Event Detected Channel n interrupt.

ValueDescription
0 The Event Detected Channel n interrupt is disabled.
1 The Event Detected Channel n interrupt is enabled.

Bits 19,18,17,16,7,6,5,4,3,2,1,0 – OVRn: Channel n Overrun Interrupt Enable [n=11..0]

Channel n Overrun Interrupt Enable [n=11..0]

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Overrun Channel n Interrupt Enable bit, which enables the Overrun Channel n interrupt.

ValueDescription
0 The Overrun Channel n interrupt is disabled.
1 The Overrun Channel n interrupt is enabled.