| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OVF | SYNCRDY | CMP1 | CMP0 | ||||
| AccessR/W | R/W | R/W | R/W | ||||
| Reset0 | 0 | 0 | 0 |
Overflow Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
| Value | Description |
|---|---|
| 0 | The Overflow interrupt is disabled. |
| 1 | The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is set. |
Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding interrupt.
| Value | Description |
|---|---|
| 0 | The Synchronization Ready interrupt is disabled. |
| 1 | The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set. |
Compare x Interrupt Enable [x=1:0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare x Interrupt Enable bit and disable the corresponding interrupt.
| Value | Description |
|---|---|
| 0 | The Compare x interrupt is disabled. |
| 1 | The Compare x interrupt is enabled, and an interrupt request will be generated when the Compare x interrupt flag is set. |