Device Variant A

The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die.

Parent topic: Errata

Die Revision A

Device

  1. In single shot mode and at 125°C, the ADC conversions have linearity errors.
    Errata reference: 13277
    Fix/Workaround:
    - Workaround 1: At 125°C, do not use the ADC in single shot mode; use the ADC in free running mode only.
    - Workaround 2: At 125°C, use the ADC in single shot mode only with VDDANA > 3V.
  2. TCC0/WO[6] on PA16 and TCC0/WO[7] on PA17 are not available.
    Errata reference: 11622
    Fix/Workaround:
    None
  3. On pin PA24 and PA25 the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled.
    Errata reference: 12368
    Fix/Workaround:
    For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them.
  4. If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible.
    Errata reference: 10416
    Fix/Workaround:
    Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin.
  5. In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset.
    Errata reference: 13574
    Fix/Workaround:
    Write CTRLB.ACKACT to 0 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Write CTRLB.ACKACT to 1 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction.
    When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position.
    Code replacements examples:
    Current:
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Current:
    SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Current:
    /* ACK or NACK address */
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
    Change to:
    // CMD=0x3 clears all interrupts, so to keep the result similar,
    // PREC is cleared if it was set.
    if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
    SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
  6. PA24 and PA25 cannot be used as input when configured as GPIO with continuous sampling (cannot be read by PORT).
    Errata reference: 12005
    Fix/Workaround:
    - Use PA24 and PA25 for peripherals or only as output pins.
    - Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes) and access the IN register through the APB (not the IOBUS), to allow waiting for on-demand sampling.
  7. The SYSTICK calibration value is incorrect.
    Errata reference: 14154
    Fix/Workaround:
    The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
  8. In Standby, Idle1 and Idle2 sleep modes the device might not wake up from sleep. An External Reset, Power on Reset or Watch Dog Reset will start the device again.
    Errata reference: 13140
    Fix/Workaround:
    the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3 (NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the device. The average power consumption of the device will increase with 20uA compared to numbers in the electrical characteristics chapter.
  9. While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all the other pins it is configured as an High Impedance pin.
    Errata reference: 12118
    Fix/Workaround:
    None
  10. Digital pin outputs from Timer/Counters, AC (Analog Comparator), GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change value during standby sleep mode.
    Errata reference: 12537
    Fix/Workaround:
    Set the voltage regulator in Normal mode before entering STANDBY sleep mode in order to keep digital pin output enabled. This is done by setting the RUNSTDBY bit in the VREG register.
  11. The I2S is non-functional.
    Errata reference: 12275
    Fix/Workaround:
    None
  12. The voltage regulator in low power mode is not functional at temperatures above 85C.
    Errata reference: 12291
    Fix/Workaround:
    Enable normal mode on the voltage regulator in standby sleep mode.
    Example code:
    // Set the voltage regulator in normal mode configuration in standby sleep mode
    SYSCTRL->VREG.bit.RUNSTDBY = 1;
  13. If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock.
    Errata reference: 12164
    Fix/Workaround:
    Do a power cycle to reset the GCLK generators after an external XOSC32K failure.

DSU

  1. If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset Extension"" after any upcoming reset event.
    Errata reference: 12015
    Fix/workaround:
    The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power cycling the device.
  2. The MBIST ""Pause-on-Error"" feature is not functional on this device.
    Errata reference: 14324
    Fix/Workaround:
    Do not use the ""Pause-on-Error"" feature.

PM

  1. In debug mode, if a watchdog reset occurs, the debug session is lost.
    Errata reference: 12196
    Fix/Workaround:
    A new debug session must be restart after a watchdog reset.

DFLL48M

  1. The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device.
    Errata reference: 9905
    Fix/Workaround:
    Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module.
  2. If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts.
    Errata reference: 10669
    Fix/Workaround:
    Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt.
  3. The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be wrong after a USB suspend state.
    Errata reference: 11938
    Fix/Workaround:
    Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode.

XOSC32K

  1. The automatic amplitude control of the XOSC32K does not work.
    Errata reference: 10933
    Fix/Workaround:
    Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0)

FDPLL

  1. The lock flag (DPLLSTATUS.LOCK) may clear randomly. When the lock flag randomly clears, DPLLLCKR and DPLLLCKF interrupts will also trigger, and the DPLL output is masked.
    Errata reference: 11791
    Fix/Workaround:
    Set DPLLCTRLB.LBYPASS to 1 to disable masking of the DPLL output by the lock status.
  2. FDPLL lock time-out values are different from the parameters in the datasheet.
    Errata reference: 12145
    Fix/Workaround:
    The time-out values are:
    - DPLLCTRLB.LTIME[2:0] = 4 : 10ms
    - DPLLCTRLB.LTIME[2:0] = 5 : 10ms
    - DPLLCTRLB.LTIME[2:0] = 6 : 11ms
    - DPLLCTRLB.LTIME[2:0] = 7 : 11ms

DMAC

  1. If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect.
    Errata reference: 13507
    Fix/Workaround:
    Add a NOP instruction between each write to CRCDATAIN register.

EIC

  1. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15341
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. Default value of MANW in NVM.CTRLB is 0.
    This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area.
    Errata reference: 13134
    Fix/Workaround:
    Set MANW in the NVM.CTRLB to 1 at startup
  2. When external reset is active it causes a high leakage current on VDDIO.
    Errata reference: 13446
    Fix/Workaround:
    Minimize the time external reset is active.
  3. When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the on-chip flash size minus half a row.
    Errata reference: 11988
    Fix/Workaround:
    When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row.

SERCOM

  1. The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested.
    Errata reference: 12003
    Fix/Workaround:
    To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-out (CTRLA.LOWTOUT=1).
  2. In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors.
    Errata reference: 13852
    Fix/Workaround:
    None
  3. If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated.
    Errata reference: 13369
    Fix/Workaround:
    Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1.
  4. In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the current byte transaction is completed and the corresponding interrupt is triggered if enabled.
    Errata reference: 12499
    Fix/Workaround:
    In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.

TC

  1. Spurious TC overflow and Match/Capture events may occur.
    Errata reference: 13268
    Fix/Workaround:
    Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead.

TCC

  1. The TCC interrupts FAULT1, FAULT0, FAULTB, FAULTA, DFS, ERR,and CNT cannot wake up the chip from standby mode.
    Errata reference: 11951
    Fix/Workaround:
    Do not use the TCC interrupts FAULT1, FAULT0, FAULTB, FAULTA, DFS, ERR, or CNT to wake up the chip from standby mode.
  2. If the OVF flag in the INTFLAG register is already set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register.
    Errata reference: 12127
    Fix/Workaround:
    None
  3. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.
  4. In RAMP 2 mode with Fault keep, qualified and restart:
    If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts.
    Errata reference: 13262
    Fix/Workaround:
    Avoid faults few cycles before the end or the beginning of a ramp.
  5. With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked.
    Errata reference: 12519
    Fix/Workaround:
    None
  6. In Dual slope mode a Retrigger Event does not clear the TCC counter.
    Errata reference: 12354
    Fix/Workaround:
    None
  7. In two ramp mode, two events will be generated per cycle, one on each ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle.
    Errata reference: 12224
    Fix/Workaround:
    None
  8. If an input event triggered STOP action is performed at the same time as the counter overflows, the first pulse width of the subsequent counter start can be altered with one prescaled clock cycle.
    Errata reference: 12107
    Fix/Workaround:
    None
  9. When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected.
    Errata reference: 12477
    Fix/Workaround:
    None.
  10. TCC fault filtering on inverted fault is not working.
    Errata reference: 12512
    Fix/Workaround:
    Use only non-inverted faults.
  11. When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB, SYNCBUSY.STATUS, SYNCBUSY.COUNT, SYNCBUSY.PATT, SYNCBUSY.WAVE, SYNCBUSY.PER and SYNCBUSY.CCx bits may be locked to 1.
    Errata reference: 12227
    Fix/Workaround:
    After waking up from STANDBY power save mode, perform a software reset of the TCC if you are using the SYNCBUSY.CTRLB, SYNCBUSY.STATUS, SYNCBUSY.COUNT, SYNCBUSY.PATT, SYNCBUSY.WAVE, SYNCBUSY.PER or SYNCBUSY.CCx bits
  12. When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or WAVEB registers will not cause a hardware exception.
    Errata reference: 11468
    Fix/Workaround:
    None
  13. If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register.
    Errata reference: 12155
    Fix/Workaround:
    None

USB

  1. The FLENC register negative sign management is not correct.
    Errata reference: 11472
    Fix/Workaround:
    The following rule must be used for negative values:
    - FLENC 8h is equal to 0 decimal.
    - FLENC 9h to Fh are equal to -1 to -7 decimal instead of -7 to -1.

PTC

  1. WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as described in the datasheet.
    Errata reference: 12860
    Fix/Workaround:
    Do not use the WCOMP interrupt. Use the WCOMP event.

Die Revision B

Device

  1. The I2S is non-functional in the slave mode (i.e. when (FSSEL=1, SCKSEL=1).
    Errata reference: 13407
    Fix/Workaround:
    None. FSSEL and SCKSEL must be 0.
  2. If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible.
    Errata reference: 10416
    Fix/Workaround:
    Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin.
  3. The software reset SWRST does not properly propagate inside the I2S module. As a consequence, the slave mode may not be reconfigured correctly and may result in unexpected behavior of the SYNCBUSY register.
    Errata reference: 12848
    Fix/workaround:
    None.
  4. PA24 and PA25 cannot be used as input when configured as GPIO with continuous sampling (cannot be read by PORT).
    Errata reference: 12005
    Fix/Workaround:
    - Use PA24 and PA25 for peripherals or only as output pins.
    - Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes) and access the IN register through the APB (not the IOBUS), to allow waiting for on-demand sampling.
  5. Rx serializer in the RIGHT Data Slot Formatting Adjust mode (SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits.
    Errata reference: 13411
    Fix/Workaround:
    In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with CLKCTRL.SLOTSIZE 32.
  6. Depending CPU clock/ I2S clock ratio, the SYNCBUSY.CKEN0 flag occasionally stuck at 1 when starting a new audio stream with CTRLA.SWRST=1, then CTRLA.ENABLE=1, then CTRLA.CKEN0=1
    Errata reference: 13408
    Fix/Workaround:
    Disable the IP by writing 0 to CTRLA.ENABLE before resetting it (CTRLA.SWRST=1).
  7. While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all the other pins it is configured as an High Impedance pin.
    Errata reference: 12118
    Fix/Workaround:
    None
  8. If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock.
    Errata reference: 12164
    Fix/Workaround:
    Do a power cycle to reset the GCLK generators after an external XOSC32K failure.
  9. In single shot mode and at 125°C, the ADC conversions have linearity errors.
    Errata reference: 13277
    Fix/Workaround:
    - Workaround 1: At 125°C, do not use the ADC in single shot mode; use the ADC in free running mode only.
    - Workaround 2: At 125°C, use the ADC in single shot mode only with VDDANA > 3V.
  10. On pin PA24 and PA25 the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled.
    Errata reference: 12368
    Fix/Workaround:
    For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them.
  11. The PDM2 mode (i.e. when using two PDM microphones) does not work.
    Errata reference: 13410
    Fix/Workaround:
    None. Only one PDM microphone can be connected. Thus, the I2S controller should be configured in normal Receive mode with one slot.
  12. In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset.
    Errata reference: 13574
    Fix/Workaround:
    Write CTRLB.ACKACT to 0 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Write CTRLB.ACKACT to 1 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction.
    When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position.
    Code replacements examples:
    Current:
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Current:
    SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Current:
    /* ACK or NACK address */
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
    Change to:
    // CMD=0x3 clears all interrupts, so to keep the result similar,
    // PREC is cleared if it was set.
    if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
    SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
  13. The SYSTICK calibration value is incorrect.
    Errata reference: 14154
    Fix/Workaround:
    The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
  14. In Standby, Idle1 and Idle2 sleep modes the device might not wake up from sleep. An External Reset, Power on Reset or Watch Dog Reset will start the device again.
    Errata reference: 13140
    Fix/Workaround:
    the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3 (NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the device. The average power consumption of the device will increase with 20uA compared to numbers in the electrical characteristics chapter.
  15. Digital pin outputs from Timer/Counters, AC (Analog Comparator), GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change value during standby sleep mode.
    Errata reference: 12537
    Fix/Workaround:
    Set the voltage regulator in Normal mode before entering STANDBY sleep mode in order to keep digital pin output enabled. This is done by setting the RUNSTDBY bit in the VREG register.
  16. The voltage regulator in low power mode is not functional at temperatures above 85C.
    Errata reference: 12291
    Fix/Workaround:
    Enable normal mode on the voltage regulator in standby sleep mode.
    Example code:
    // Set the voltage regulator in normal mode configuration in standby sleep mode
    SYSCTRL->VREG.bit.RUNSTDBY = 1;

DSU

  1. If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset Extension"" after any upcoming reset event.
    Errata reference: 12015
    Fix/workaround:
    The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power cycling the device.
  2. The MBIST ""Pause-on-Error"" feature is not functional on this device.
    Errata reference: 14324
    Fix/Workaround:
    Do not use the ""Pause-on-Error"" feature.

PM

  1. In debug mode, if a watchdog reset occurs, the debug session is lost.
    Errata reference: 12196
    Fix/Workaround:
    A new debug session must be restart after a watchdog reset.

DFLL48M

  1. The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device.
    Errata reference: 9905
    Fix/Workaround:
    Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module.
  2. If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts.
    Errata reference: 10669
    Fix/Workaround:
    Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt.
  3. The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be wrong after a USB suspend state.
    Errata reference: 11938
    Fix/Workaround:
    Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode.

XOSC32K

  1. The automatic amplitude control of the XOSC32K does not work.
    Errata reference: 10933
    Fix/Workaround:
    Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0)

DMAC

  1. If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect.
    Errata reference: 13507
    Fix/Workaround:
    Add a NOP instruction between each write to CRCDATAIN register.

EIC

  1. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15341
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. Default value of MANW in NVM.CTRLB is 0.
    This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area.
    Errata reference: 13134
    Fix/Workaround:
    Set MANW in the NVM.CTRLB to 1 at startup
  2. When external reset is active it causes a high leakage current on VDDIO.
    Errata reference: 13446
    Fix/Workaround:
    Minimize the time external reset is active.
  3. When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the on-chip flash size minus half a row.
    Errata reference: 11988
    Fix/Workaround:
    When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row.

SERCOM

  1. The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested.
    Errata reference: 12003
    Fix/Workaround:
    To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-out (CTRLA.LOWTOUT=1).
  2. In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors.
    Errata reference: 13852
    Fix/Workaround:
    None
  3. If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated.
    Errata reference: 13369
    Fix/Workaround:
    Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1.
  4. In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the current byte transaction is completed and the corresponding interrupt is triggered if enabled.
    Errata reference: 12499
    Fix/Workaround:
    In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.

TC

  1. Spurious TC overflow and Match/Capture events may occur.
    Errata reference: 13268
    Fix/Workaround:
    Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead.

TCC

  1. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.
  2. In RAMP 2 mode with Fault keep, qualified and restart:
    If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts.
    Errata reference: 13262
    Fix/Workaround:
    Avoid faults few cycles before the end or the beginning of a ramp.
  3. With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked.
    Errata reference: 12519
    Fix/Workaround:
    None
  4. In Dual slope mode a Retrigger Event does not clear the TCC counter.
    Errata reference: 12354
    Fix/Workaround:
    None
  5. In two ramp mode, two events will be generated per cycle, one on each ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle.
    Errata reference: 12224
    Fix/Workaround:
    None
  6. If an input event triggered STOP action is performed at the same time as the counter overflows, the first pulse width of the subsequent counter start can be altered with one prescaled clock cycle.
    Errata reference: 12107
    Fix/Workaround:
    None
  7. When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected.
    Errata reference: 12477
    Fix/Workaround:
    None.
  8. TCC fault filtering on inverted fault is not working.
    Errata reference: 12512
    Fix/Workaround:
    Use only non-inverted faults.
  9. When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB, SYNCBUSY.STATUS, SYNCBUSY.COUNT, SYNCBUSY.PATT, SYNCBUSY.WAVE, SYNCBUSY.PER and SYNCBUSY.CCx bits may be locked to 1.
    Errata reference: 12227
    Fix/Workaround:
    After waking up from STANDBY power save mode, perform a software reset of the TCC if you are using the SYNCBUSY.CTRLB, SYNCBUSY.STATUS, SYNCBUSY.COUNT, SYNCBUSY.PATT, SYNCBUSY.WAVE, SYNCBUSY.PER or SYNCBUSY.CCx bits
  10. When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or WAVEB registers will not cause a hardware exception.
    Errata reference: 11468
    Fix/Workaround:
    None
  11. If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register.
    Errata reference: 12155
    Fix/Workaround:
    None

PTC

  1. WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as described in the datasheet.
    Errata reference: 12860
    Fix/Workaround:
    Do not use the WCOMP interrupt. Use the WCOMP event.

Die Revision C

Device

  1. In single shot mode and at 125°C, the ADC conversions have linearity errors.
    Errata reference: 13277
    Fix/Workaround:
    - Workaround 1: At 125°C, do not use the ADC in single shot mode; use the ADC in free running mode only.
    - Workaround 2: At 125°C, use the ADC in single shot mode only with VDDANA > 3V.
  2. In the table ""NVM User Row Mapping"", the WDT Window bitfield default value on silicon is not as specified in the datasheet. The datasheet defines the default value as 0x5, while it is 0xB on silicon.
    Errata reference: 13951
    Fix/Workaround:
    None.
  3. On pin PA24 and PA25 the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled.
    Errata reference: 12368
    Fix/Workaround:
    For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them.
  4. If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible.
    Errata reference: 10416
    Fix/Workaround:
    Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin.
  5. In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset.
    Errata reference: 13574
    Fix/Workaround:
    Write CTRLB.ACKACT to 0 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Write CTRLB.ACKACT to 1 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction.
    When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position.
    Code replacements examples:
    Current:
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Current:
    SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Current:
    /* ACK or NACK address */
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
    Change to:
    // CMD=0x3 clears all interrupts, so to keep the result similar,
    // PREC is cleared if it was set.
    if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
    SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
  6. PA24 and PA25 cannot be used as input when configured as GPIO with continuous sampling (cannot be read by PORT).
    Errata reference: 12005
    Fix/Workaround:
    - Use PA24 and PA25 for peripherals or only as output pins.
    - Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes) and access the IN register through the APB (not the IOBUS), to allow waiting for on-demand sampling.
  7. Rx serializer in the RIGHT Data Slot Formatting Adjust mode (SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits.
    Errata reference: 13411
    Fix/Workaround:
    In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with CLKCTRL.SLOTSIZE 32.
  8. The SYSTICK calibration value is incorrect.
    Errata reference: 14154
    Fix/Workaround:
    The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
  9. In Standby, Idle1 and Idle2 sleep modes the device might not wake up from sleep. An External Reset, Power on Reset or Watch Dog Reset will start the device again.
    Errata reference: 13140
    Fix/Workaround:
    the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3 (NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the device. The average power consumption of the device will increase with 20uA compared to numbers in the electrical characteristics chapter.
  10. While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all the other pins it is configured as an High Impedance pin.
    Errata reference: 12118
    Fix/Workaround:
    None
  11. The voltage regulator in low power mode is not functional at temperatures above 85C.
    Errata reference: 12291
    Fix/Workaround:
    Enable normal mode on the voltage regulator in standby sleep mode.
    Example code:
    // Set the voltage regulator in normal mode configuration in standby sleep mode
    SYSCTRL->VREG.bit.RUNSTDBY = 1;
  12. If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock.
    Errata reference: 12164
    Fix/Workaround:
    Do a power cycle to reset the GCLK generators after an external XOSC32K failure.

DSU

  1. If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset Extension"" after any upcoming reset event.
    Errata reference: 12015
    Fix/workaround:
    The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power cycling the device.
  2. The MBIST ""Pause-on-Error"" feature is not functional on this device.
    Errata reference: 14324
    Fix/Workaround:
    Do not use the ""Pause-on-Error"" feature.

PM

  1. In debug mode, if a watchdog reset occurs, the debug session is lost.
    Errata reference: 12196
    Fix/Workaround:
    A new debug session must be restart after a watchdog reset.

DFLL48M

  1. The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device.
    Errata reference: 9905
    Fix/Workaround:
    Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module.
  2. If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts.
    Errata reference: 10669
    Fix/Workaround:
    Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt.
  3. The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be wrong after a USB suspend state.
    Errata reference: 11938
    Fix/Workaround:
    Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode.

XOSC32K

  1. The automatic amplitude control of the XOSC32K does not work.
    Errata reference: 10933
    Fix/Workaround:
    Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0)

DMAC

  1. If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect.
    Errata reference: 13507
    Fix/Workaround:
    Add a NOP instruction between each write to CRCDATAIN register.

EIC

  1. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15341
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. Default value of MANW in NVM.CTRLB is 0.
    This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area.
    Errata reference: 13134
    Fix/Workaround:
    Set MANW in the NVM.CTRLB to 1 at startup
  2. When external reset is active it causes a high leakage current on VDDIO.
    Errata reference: 13446
    Fix/Workaround:
    Minimize the time external reset is active.
  3. When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the on-chip flash size minus half a row.
    Errata reference: 11988
    Fix/Workaround:
    When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row.

I2S

  1. I2S RX serializer in LSBIT mode (SERCTRL.BITREV set) only works when the slot size is 32 bits.
    Errata reference: 13320
    Fix/Workaround:
    In SERCTRL.SERMODE RX, SERCTRL.BITREV LSBIT must be used with CLKCTRL.SLOTSIZE 32.

SERCOM

  1. The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested.
    Errata reference: 12003
    Fix/Workaround:
    To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-out (CTRLA.LOWTOUT=1).
  2. In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors.
    Errata reference: 13852
    Fix/Workaround:
    None
  3. If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated.
    Errata reference: 13369
    Fix/Workaround:
    Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1.
  4. In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the current byte transaction is completed and the corresponding interrupt is triggered if enabled.
    Errata reference: 12499
    Fix/Workaround:
    In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.

TC

  1. Spurious TC overflow and Match/Capture events may occur.
    Errata reference: 13268
    Fix/Workaround:
    Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead.

TCC

  1. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.
  2. In RAMP 2 mode with Fault keep, qualified and restart:
    If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts.
    Errata reference: 13262
    Fix/Workaround:
    Avoid faults few cycles before the end or the beginning of a ramp.
  3. With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked.
    Errata reference: 12519
    Fix/Workaround:
    None
  4. In Dual slope mode a Retrigger Event does not clear the TCC counter.
    Errata reference: 12354
    Fix/Workaround:
    None
  5. In two ramp mode, two events will be generated per cycle, one on each ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle.
    Errata reference: 12224
    Fix/Workaround:
    None
  6. If an input event triggered STOP action is performed at the same time as the counter overflows, the first pulse width of the subsequent counter start can be altered with one prescaled clock cycle.
    Errata reference: 12107
    Fix/Workaround:
    None
  7. When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected.
    Errata reference: 12477
    Fix/Workaround:
    None.
  8. TCC fault filtering on inverted fault is not working.
    Errata reference: 12512
    Fix/Workaround:
    Use only non-inverted faults.
  9. When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB, SYNCBUSY.STATUS, SYNCBUSY.COUNT, SYNCBUSY.PATT, SYNCBUSY.WAVE, SYNCBUSY.PER and SYNCBUSY.CCx bits may be locked to 1.
    Errata reference: 12227
    Fix/Workaround:
    After waking up from STANDBY power save mode, perform a software reset of the TCC if you are using the SYNCBUSY.CTRLB, SYNCBUSY.STATUS, SYNCBUSY.COUNT, SYNCBUSY.PATT, SYNCBUSY.WAVE, SYNCBUSY.PER or SYNCBUSY.CCx bits
  10. When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or WAVEB registers will not cause a hardware exception.
    Errata reference: 11468
    Fix/Workaround:
    None
  11. If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register.
    Errata reference: 12155
    Fix/Workaround:
    None

PTC

  1. WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as described in the datasheet.
    Errata reference: 12860
    Fix/Workaround:
    Do not use the WCOMP interrupt. Use the WCOMP event.

Die Revision D

Device

  1. In single shot mode and at 125°C, the ADC conversions have linearity errors.
    Errata reference: 13277
    Fix/Workaround:
    - Workaround 1: At 125°C, do not use the ADC in single shot mode; use the ADC in free running mode only.
    - Workaround 2: At 125°C, use the ADC in single shot mode only with VDDANA > 3V.
  2. In the table ""NVM User Row Mapping"", the WDT Window bitfield default value on silicon is not as specified in the datasheet. The datasheet defines the default value as 0x5, while it is 0xB on silicon.
    Errata reference: 13951
    Fix/Workaround:
    None.
  3. On pin PA24 and PA25 the pull-up and pull-down configuration is not disabled automatically when alternative pin function is enabled.
    Errata reference: 12368
    Fix/Workaround:
    For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before enabling alternative functions on them.
  4. If APB clock is stopped and GCLK clock is running, APB read access to read-synchronized registers will freeze the system. The CPU and the DAP AHB-AP are stalled, as a consequence debug operation is impossible.
    Errata reference: 10416
    Fix/Workaround:
    Do not make read access to read-synchronized registers when APB clock is stopped and GCLK is running. To recover from this situation, power cycle the device or reset the device using the RESETN pin.
  5. In I2C Slave mode, writing the CTRLB register when in the AMATCH or DRDY interrupt service routines can cause the state machine to reset.
    Errata reference: 13574
    Fix/Workaround:
    Write CTRLB.ACKACT to 0 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Write CTRLB.ACKACT to 1 using the following sequence:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close out a transaction.
    When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit position instead of using CTRLB.CMD. The DRDY interrupt is automatically cleared by reading/writing to the DATA register in smart mode. If not in smart mode, DRDY should be cleared by writing a 1 to its bit position.
    Code replacements examples:
    Current:
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
    // Re-enable interrupts if applicable.
    Current:
    SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
    Change to:
    // If higher priority interrupts exist, then disable so that the
    // following two writes are atomic.
    SERCOM - STATUS.reg = 0;
    SERCOM - CTRLB.reg = 0;
    // Re-enable interrupts if applicable.
    Current:
    /* ACK or NACK address */
    SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
    Change to:
    // CMD=0x3 clears all interrupts, so to keep the result similar,
    // PREC is cleared if it was set.
    if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
    SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
  6. PA24 and PA25 cannot be used as input when configured as GPIO with continuous sampling (cannot be read by PORT).
    Errata reference: 12005
    Fix/Workaround:
    - Use PA24 and PA25 for peripherals or only as output pins.
    - Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes) and access the IN register through the APB (not the IOBUS), to allow waiting for on-demand sampling.
  7. Rx serializer in the RIGHT Data Slot Formatting Adjust mode (SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits.
    Errata reference: 13411
    Fix/Workaround:
    In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with CLKCTRL.SLOTSIZE 32.
  8. The SYSTICK calibration value is incorrect.
    Errata reference: 14154
    Fix/Workaround:
    The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize the Systick RELOAD value register, which should be initialized instead with a value depending on the main clock frequency and on the tick period required by the application. For a detailed description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
  9. While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all the other pins it is configured as an High Impedance pin.
    Errata reference: 12118
    Fix/Workaround:
    None
  10. If the external XOSC32K is broken, neither the external pin RST nor the GCLK software reset can reset the GCLK generators using XOSC32K as source clock.
    Errata reference: 12164
    Fix/Workaround:
    Do a power cycle to reset the GCLK generators after an external XOSC32K failure.
  11. The voltage regulator in low power mode is not functional at temperatures above 85C.
    Errata reference: 12291
    Fix/Workaround:
    Enable normal mode on the voltage regulator in standby sleep mode.
    Example code:
    // Set the voltage regulator in normal mode configuration in standby sleep mode
    SYSCTRL->VREG.bit.RUNSTDBY = 1;

DSU

  1. If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset Extension"" after any upcoming reset event.
    Errata reference: 12015
    Fix/workaround:
    The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power cycling the device.
  2. The MBIST ""Pause-on-Error"" feature is not functional on this device.
    Errata reference: 14324
    Fix/Workaround:
    Do not use the ""Pause-on-Error"" feature.

PM

  1. In debug mode, if a watchdog reset occurs, the debug session is lost.
    Errata reference: 12196
    Fix/Workaround:
    A new debug session must be restart after a watchdog reset.

DFLL48M

  1. The DFLL clock must be requested before being configured otherwise a write access to a DFLL register can freeze the device.
    Errata reference: 9905
    Fix/Workaround:
    Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL module.
  2. If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values during the locking sequence, an out of bounds interrupt will be generated. These interrupts will be generated even if the final calibration values at DFLL48M lock are not at maximum or minimum, and might therefore be false out of bounds interrupts.
    Errata reference: 10669
    Fix/Workaround:
    Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt.
  3. The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be wrong after a USB suspend state.
    Errata reference: 11938
    Fix/Workaround:
    Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode.

XOSC32K

  1. The automatic amplitude control of the XOSC32K does not work.
    Errata reference: 10933
    Fix/Workaround:
    Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0)

DMAC

  1. If data is written to CRCDATAIN in two consecutive instructions, the CRC computation may be incorrect.
    Errata reference: 13507
    Fix/Workaround:
    Add a NOP instruction between each write to CRCDATAIN register.

EIC

  1. When the EIC is configured to generate an interrupt on a low level or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled (CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using CTRLA ENABLE bit.
    Errata reference: 15341
    Fix/Workaround:
    Clear the INTFLAG bit once the EIC enabled and before enabling the interrupts.

NVMCTRL

  1. Default value of MANW in NVM.CTRLB is 0.
    This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong address corresponding to NVM area.
    Errata reference: 13134
    Fix/Workaround:
    Set MANW in the NVM.CTRLB to 1 at startup
  2. When external reset is active it causes a high leakage current on VDDIO.
    Errata reference: 13446
    Fix/Workaround:
    Minimize the time external reset is active.
  3. When the part is secured and EEPROM emulation area configured to none, the CRC32 is not executed on the entire flash area but up to the on-chip flash size minus half a row.
    Errata reference: 11988
    Fix/Workaround:
    When using CRC32 on a protected device with EEPROM emulation area configured to none, compute the reference CRC32 value to the full chip flash size minus half row.

I2S

  1. I2S RX serializer in LSBIT mode (SERCTRL.BITREV set) only works when the slot size is 32 bits.
    Errata reference: 13320
    Fix/Workaround:
    In SERCTRL.SERMODE RX, SERCTRL.BITREV LSBIT must be used with CLKCTRL.SLOTSIZE 32.

SERCOM

  1. The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is not requested.
    Errata reference: 12003
    Fix/Workaround:
    To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-out (CTRLA.LOWTOUT=1).
  2. In USART autobaud mode, missing stop bits are not recognized as inconsistent sync (ISF) or framing (FERR) errors.
    Errata reference: 13852
    Fix/Workaround:
    None
  3. If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated.
    Errata reference: 13369
    Fix/Workaround:
    Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1.
  4. In TWI master mode, an ongoing transaction should be stalled immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the current byte transaction is completed and the corresponding interrupt is triggered if enabled.
    Errata reference: 12499
    Fix/Workaround:
    In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.

TC

  1. Spurious TC overflow and Match/Capture events may occur.
    Errata reference: 13268
    Fix/Workaround:
    Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead.

TCC

  1. Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX DERIV0) doesn’t work if an upper channel is not in one of these mode. Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN, and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
    Errata reference: 14817
    Fix/Workaround:
    Basic capture mode must be set in lower channel and advance capture mode in upper channel.
    Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN, CC[3]=CAPTMAX
    All capture will be done as expected.
  2. In RAMP 2 mode with Fault keep, qualified and restart:
    If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can have two restarts.
    Errata reference: 13262
    Fix/Workaround:
    Avoid faults few cycles before the end or the beginning of a ramp.
  3. With blanking enabled, a recoverable fault that occurs during the first increment of a rising TCC is not blanked.
    Errata reference: 12519
    Fix/Workaround:
    None
  4. In Dual slope mode a Retrigger Event does not clear the TCC counter.
    Errata reference: 12354
    Fix/Workaround:
    None
  5. In two ramp mode, two events will be generated per cycle, one on each ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle.
    Errata reference: 12224
    Fix/Workaround:
    None
  6. If an input event triggered STOP action is performed at the same time as the counter overflows, the first pulse width of the subsequent counter start can be altered with one prescaled clock cycle.
    Errata reference: 12107
    Fix/Workaround:
    None
  7. When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected.
    Errata reference: 12477
    Fix/Workaround:
    None.
  8. TCC fault filtering on inverted fault is not working.
    Errata reference: 12512
    Fix/Workaround:
    Use only non-inverted faults.
  9. When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB, SYNCBUSY.STATUS, SYNCBUSY.COUNT, SYNCBUSY.PATT, SYNCBUSY.WAVE, SYNCBUSY.PER and SYNCBUSY.CCx bits may be locked to 1.
    Errata reference: 12227
    Fix/Workaround:
    After waking up from STANDBY power save mode, perform a software reset of the TCC if you are using the SYNCBUSY.CTRLB, SYNCBUSY.STATUS, SYNCBUSY.COUNT, SYNCBUSY.PATT, SYNCBUSY.WAVE, SYNCBUSY.PER or SYNCBUSY.CCx bits
  10. When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or WAVEB registers will not cause a hardware exception.
    Errata reference: 11468
    Fix/Workaround:
    None
  11. If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an immediate DMA transfer and overwrite the current buffered value in the TCC register.
    Errata reference: 12155
    Fix/Workaround:
    None

PTC

  1. WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as described in the datasheet.
    Errata reference: 12860
    Fix/Workaround:
    Do not use the WCOMP interrupt. Use the WCOMP event.