Status
Name:
STATUS
Offset:
0x0F
Reset:
0x08
Access:
-
Bit76543210
SYNCBUSYSLAVESTOP
AccessRRR
Reset001

Bit 7 – SYNCBUSY: Synchronization Busy

Synchronization Busy

This bit is cleared when the synchronization of registers between the clock domains is complete.

This bit is set when the synchronization of registers between clock domains is started.

Bit 4 – SLAVE: Slave Status Flag

Slave Status Flag

This bit is only available in 32-bit mode on the slave TC (i.e., TC1 and/or TC3). The bit is set when the associated master TC (TC0 and TC2, respectively) is set to run in 32-bit mode.

Bit 3 – STOP: Stop Status Flag

Stop Status Flag

This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.

ValueDescription
0 Counter is running.
1 Counter is stopped.