Analog-to-Digital (ADC) characteristics

Table 1. Operating Conditions
Symbol Parameter Conditions Min. Typ. Max. Units
RES Resolution   8 - 12 bits
fCLK_ADC ADC Clock frequency   30 - 2100 kHz
  Sample rate(1) Single shot 5 - 300 ksps
Free running 5 - 350 ksps
  Sampling time(1)   0.5 - - cycles
  Conversion time(1) 1x Gain 6 - - cycles
VREF Voltage reference range   1.0 - VDDANA-0.6 V
VREFINT1V Internal 1V reference (2)   - 1.0 - V
VREFINTVCC0 Internal ratiometric reference 0(2)   - VDDANA/1.48 - V
VREFINTVCC0 Voltage Error Internal ratiometric reference 0(2) error 2.0V < VDDANA<3.63V -1.0 - +1.0 %
VREFINTVCC1 Internal ratiometric reference 1(2) VDDANA>2.0V - VDDANA/2 - V
VREFINTVCC1 Voltage Error Internal ratiometric reference 1(2) error 2.0V < VDDANA<3.63V -1.0 - +1.0 %
  Conversion range(1) Differential mode -VREF/GAIN - +VREF/GAIN V
Single-ended mode 0.0 - +VREF/GAIN V
CSAMPLE Sampling capacitance(2)   - 3.5 - pF
RSAMPLE Input channel source resistance(2)   - - 3.5 kΩ
IDD DC supply current(1) fCLK_ADC = 2.1MHz(3) - 1.25 1.79 mA
Note:
  1. These values are based on characterization. These values are not covered by test limits in production.
  2. These values are based on simulation. These values are not covered by test limits in production or characterization.
  3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC clock.
Table 2. Differential Mode (Device Variant A)
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number Of Bits With gain compensation - 10.5 11.1 bits
TUE Total Unadjusted Error 1x gain 1.5 4.3 15.0 LSB
INLI Integral Non Linearity 1x gain 1.0 1.3 4.5 LSB
DNL Differential Non Linearity 1x gain +/-0.3 +/-0.5 +/-0.95 LSB

Gain Error Ext. Ref 1x -10.0 2.5 +10.0 mV
VREF=VDDANA/1.48 -15.0 -1.5 +10.0 mV
Bandgap -20.0 -5.0 +20.0 mV
  Gain Accuracy(5) Ext. Ref. 0.5x +/-0.1 +/-0.2 +/-0.45 %
Ext. Ref. 2x to 16x +/-0.05 +/-0.1 +/-0.11 %
  Offset Error Ext. Ref. 1x -5.0 -1.5 +5.0 mV
VREF=VDDANA/1.48 -5.0 0.5 +5.0 mV
Bandgap -5.0 3.0 +5.0 mV
SFDR Spurious Free Dynamic Range 1x Gain

FCLK_ADC = 2.1MHz

FIN = 40kHz

AIN = 95%FSR

 62.7 70.0 75.0 dB
SINAD Signal-to-Noise and Distortion 54.1 65.0 68.5 dB
SNR Signal-to-Noise Ratio 54.5 65.5 68.6 dB
THD Total Harmonic Distortion -77.0 -64.0 -63.0 dB
  Noise RMS T=25°C 0.6 1.0 1.6 mV
Table 3. Differential Mode (Device Variant B)
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number Of Bits With gain compensation - 10.5 10.8 bits
TUE Total Unadjusted Error 1x gain 1.5 2.7 10.0 LSB
INLI Integral Non Linearity 1x gain 0.9 1.3 4.0 LSB
DNL Differential Non Linearity 1x gain +/-0.3 +/-0.5 +/-0.95 LSB
  Gain Error Ext. Ref 1x -10.0 1.3 +10.0 mV
VREF=VDDANA/1.48 -10.0 -1.0 +10.0 mV
Bandgap -20.0 -2.0 +20.0 mV
  Gain Accuracy(5) Ext. Ref. 0.5x +/-0.02 +/-0.05 +/-0.1 %
Ext. Ref. 2x to 16x +/-0.01 +/-0.03 +/-0.5 %
  Offset Error Ext. Ref. 1x -5.0 -1.0 +5.0 mV
VREF=VDDANA/1.48 -5.0 0.6 +5.0 mV
Bandgap -5.0 -1.0 +5.0 mV
SFDR Spurious Free Dynamic Range 1x gain

FCLK_ADC = 2.1MHz

FIN = 40kHz

AIN = 95%FSR

 65 71.3 77.0 dB
SINAD Signal-to-Noise and Distortion 58 65 67 dB
SNR Signal-to-Noise Ratio 60 66 68.6 dB
THD Total Harmonic Distortion -75.0 -71.0 -67.0 dB
  Noise RMS T=25°C 0.6 1.0 1.6 mV
Note:
  1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input voltage range.
  2. Dynamic parameter numbers are based on characterization and not tested in production.
  3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage):
      1. If |VIN| > VREF/4
        • VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
        • VCM_IN > VREF/4 -0.05*VDDANA -0.1V
      2. If |VIN| < VREF/4
        • VCM_IN < 1.2*VDDANA - 0.75V
        • VCM_IN > 0.2*VDDANA - 0.1V
  4. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
  5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (2*Vref/GAIN)
Table 4. Single-Ended Mode (Device Variant A)
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number of Bits With gain compensation - 9.5 9.8 Bits
TUE Total Unadjusted Error 1x gain - 10.5 14.0 LSB
INL Integral Non-Linearity 1x gain 1.0 1.6 3.5 LSB
DNL Differential Non-Linearity 1x gain +/-0.5 +/-0.6 +/-0.95 LSB
  Gain Error Ext. Ref. 1x -5.0 0.7 +5.0 mV
  Gain Accuracy(4) Ext. Ref. 0.5x +/-0.2 +/-0.34 +/-0.4 %
  Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0.2 %
  Offset Error Ext. Ref. 1x -5.0 1.5 +5.0 mV
SFDR Spurious Free Dynamic Range 1x gain

FCLK_ADC = 2.1MHz

FIN = 40kHz

AIN = 95%FSR

 63.1 65.0 67.0 dB
SINAD Signal-to-Noise and Distortion 47.5 59.5 61.0 dB
SNR Signal-to-Noise Ratio 48.0 60.0 64.0 dB
THD Total Harmonic Distortion -65.4 -63.0 -62.1 dB
  Noise RMS T = 25°C - 1.0 - mV
Table 5. Single-Ended Mode (Device Variant B)
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number of Bits With gain compensation - 9.7 10.1 Bits
TUE Total Unadjusted Error 1x gain - 7.9 15.0 LSB
INL Integral Non-Linearity 1x gain 1.4 2.6 4.5 LSB
DNL Differential Non-Linearity 1x gain +/-0.6 +/-0.7 +/-0.95 LSB
  Gain Error Ext. Ref. 1x -5.0 0.6 +5.0 mV
  Gain Accuracy(4) Ext. Ref. 0.5x +/-0.2 +/-0.37 +/-0.55 %
  Ext. Ref. 2x to 16X +/-0.01 +/-0.1 +/-0.2 %
  Offset Error Ext. Ref. 1x -5.0 0.6 +5.0 mV
SFDR Spurious Free Dynamic Range 1x gain

FCLK_ADC = 2.1MHz

FIN = 40kHz

AIN = 95%FSR

 63.0 68.0 71.0 dB
SINAD Signal-to-Noise and Distortion 55.0 60.1 63.0 dB
SNR Signal-to-Noise Ratio 54.0 61.0 64.0 dB
THD Total Harmonic Distortion -70.8 -68.0 -65.0 dB
  Noise RMS T = 25°C - 1.0 - mV
Note:
  1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage range.
  2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage) for all VIN:
    • VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
    • VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
  3. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC performance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
  4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) / (Vref/GAIN)
Parent topic: Analog Characteristics