Device EndPoint Interrupt Flag n
Name:
EPINTFLAGn
Offset:
0x107 + (n x 0x20)
Reset:
0x00
Access:
-
Bit76543210
STALLRXSTPTRFAILTRCPT
AccessR/WR/WR/WR/W
Reset0000

Bit 5 – STALL: Transmit Stall x Interrupt Flag

Transmit Stall x Interrupt Flag

This flag is cleared by writing a one to the flag.

This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL is one.

EPINTFLAG.STALL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".

Writing a zero to this bit has no effect.

Writing a one to this bit clears the STALL Interrupt Flag.

Bit 4 – RXSTP: Received Setup Interrupt Flag

Received Setup Interrupt Flag

This flag is cleared by writing a one to the flag.

This flag is set when a Received Setup occurs and will generate an interrupt if EPINTENCLR/SET.RXSTP is one.

Writing a zero to this bit has no effect.

Writing a one to this bit clears the RXSTP Interrupt Flag.

Bit 2 – TRFAIL: Transfer Fail x Interrupt Flag

Transfer Fail x Interrupt Flag

This flag is cleared by writing a one to the flag.

This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL is one.

EPINTFLAG.TRFAIL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".

Writing a zero to this bit has no effect.

Writing a one to this bit clears the TRFAIL Interrupt Flag.

Bit 0 – TRCPT: Transfer Complete x interrupt Flag

Transfer Complete x interrupt Flag

This flag is cleared by writing a one to the flag.

This flag is set when a Transfer complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT is one. EPINTFLAG.TRCPT is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".

Writing a zero to this bit has no effect.

Writing a one to this bit clears the TRCPT0 Interrupt Flag.