Due to asynchronicity between the main clock
domain and the peripheral clock domains, some registers need to be synchronized when
written or read.
When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires
synchronization is executed while the corresponding SYNCBUSY bit is '1', a peripheral bus
error is generated.
The following bits are synchronized when written:
- Software Reset bit in the Control A
register (CTRLA.SWRST). SYNCBUSY.SWRST is set to '1' while synchronization is in
progress.
- Enable bit in the Control A register
(CTRLA.ENABLE). SYNCBUSY.ENABLE is set to '1' while synchronization is in progress.
- Clock Unit x Enable bits in the Control
A register (CTRLA.CKENx). SYNCBUSY.CKENx is set to '1' while synchronization is in
progress.
- Serializer x Enable bits in the Control A register
(CTRLA.SERENx). SYNCBUSY.SERENx is set to '1' while
synchronization is in progress.
The following registers require synchronization when read or written:
- Data n registers
(DATAn), Read-Synchronized when Serializer n is in Rx mode or Write-Synchronized when
in Tx mode. SYNCBUSY.DATAn is set to '1' while synchronization is in progress.
Synchronization is denoted by the Read-Synchronized or Write-Synchronized property in the register description.