| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DPLLLTO | DPLLLCKF | ||||||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DPLLLCKR | B33SRDY | BOD33DET | BOD33RDY | DFLLRCS | |||
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DFLLLCKC | DFLLLCKF | DFLLOOB | DFLLRDY | OSC8MRDY | OSC32KRDY | XOSC32KRDY | XOSCRDY |
| AccessR | R | R | R | R | R | R | R |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
DPLL Lock Timeout
| Value | Description |
|---|---|
| 0 | DPLL Lock time-out not detected. |
| 1 | DPLL Lock time-out detected. |
DPLL Lock Fall
| Value | Description |
|---|---|
| 0 | DPLL Lock fall edge not detected. |
| 1 | DPLL Lock fall edge detected. |
DPLL Lock Rise
| Value | Description |
|---|---|
| 0 | DPLL Lock rise edge not detected. |
| 1 | DPLL Lock fall edge detected. |
BOD33 Synchronization Ready
| Value | Description |
|---|---|
| 0 | BOD33 synchronization is complete. |
| 1 | BOD33 synchronization is ongoing. |
BOD33 Detection
| Value | Description |
|---|---|
| 0 | No BOD33 detection. |
| 1 | BOD33 has detected that the I/O power supply is going below the BOD33 reference value. |
BOD33 Ready
| Value | Description |
|---|---|
| 0 | BOD33 is not ready. |
| 1 | BOD33 is ready. |
DFLL Reference Clock Stopped
| Value | Description |
|---|---|
| 0 | DFLL reference clock is running. |
| 1 | DFLL reference clock has stopped. |
DFLL Lock Coarse
| Value | Description |
|---|---|
| 0 | No DFLL coarse lock detected. |
| 1 | DFLL coarse lock detected. |
DFLL Lock Fine
| Value | Description |
|---|---|
| 0 | No DFLL fine lock detected. |
| 1 | DFLL fine lock detected. |
DFLL Out Of Bounds
| Value | Description |
|---|---|
| 0 | No DFLL Out Of Bounds detected. |
| 1 | DFLL Out Of Bounds detected. |
DFLL Ready
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
| Value | Description |
|---|---|
| 0 | The Synchronization is ongoing. |
| 1 | The Synchronization is complete. |
OSC8M Ready
| Value | Description |
|---|---|
| 0 | OSC8M is not ready. |
| 1 | OSC8M is stable and ready to be used as a clock source. |
OSC32K Ready
| Value | Description |
|---|---|
| 0 | OSC32K is not ready. |
| 1 | OSC32K is stable and ready to be used as a clock source. |
XOSC32K Ready
| Value | Description |
|---|---|
| 0 | XOSC32K is not ready. |
| 1 | XOSC32K is stable and ready to be used as a clock source. |
XOSC Ready
| Value | Description |
|---|---|
| 0 | XOSC is not ready. |
| 1 | XOSC is stable and ready to be used as a clock source. |