Based on sampling frequency
fs, the
SCKn frequency requirement can be calculated:
- SCKn frequency:
fSCKn=fs× total_number_of_bits_per_frame,
- Where total_number_of_bits_per_frame= number_of_slots × number_of_bits_per_slots.
- The number of slots is selected by
writing to the Number of Slots in Frame bit field in the Clock Unit n Control
(CLKCTRLn) register: number_of_slots= NBSLOTS + 1.
- The number of bits per slot (8, 16,
24, or 32 bit) is selected by writing to the Slot Size bit field in CLKCTRLn:
number_of_bits_per_slot=8×(SLOTSIZE+1).
- Consequently, fSCKn=8×fs×(NBSLOTS+1)×(SLOTSIZE+1).
The clock frequencies
fSCKn and
fMCKn are derived from the generic clock frequency
fGCLK_I2S_n :
Substituting the right hand sides of the two last equations yields:
fMCKn=fGCLK_I2S_nMCKOUTDIV+1
fMCKn=8⋅(SLOTSIZE+1)⋅(NBSLOTS+1)⋅(MCKDIV+1)MCKOUTDIV+1
If a Master Clock output is not required,
the GCLK_I2S generic clock can be configured as SCKn by writing a '0'to CLKCTRLn.MCKDIV.
Alternatively, if the frequency of the generic clock is a multiple of the required SCKn
frequency, the MCKn-to-SCKn divider can be used with the ratio defined by writing the
CLKCTRLn.MCKDIV field.
The FSn pin is used as Word Select in
I2S format and as Frame Synchronization in TDM format, as described in I2S Format - Reception and Transmission Sequence with Word Select and TDM Format - Reception and Transmission Sequence, respectively.