| Bit31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EVD11 | EVD10 | EVD9 | EVD8 | ||||
| Access | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | |||
| Bit23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| OVR11 | OVR10 | OVR9 | OVR8 | ||||
| Access | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | |||
| Bit15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EVD7 | EVD6 | EVD5 | EVD4 | EVD3 | EVD2 | EVD1 | EVD0 |
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OVR7 | OVR6 | OVR5 | OVR4 | OVR3 | OVR2 | OVR1 | OVR0 |
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Channel n Event Detection Interrupt Enable [n=11..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n Interrupt Enable bit, which disables the Event Detected Channel n interrupt.
| Value | Description |
|---|---|
| 0 | The Event Detected Channel n interrupt is disabled. |
| 1 | The Event Detected Channel n interrupt is enabled. |
Channel n Overrun Interrupt Enable [n=11..0]
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Channel n Interrupt Enable bit, which disables the Overrun Channel n interrupt.
| Value | Description |
|---|---|
| 0 | The Overrun Channel n interrupt is disabled. |
| 1 | The Overrun Channel n interrupt is enabled. |