Contents

Introduction Features Description Configuration Summary Ordering Information SAM D21E SAM D21G SAM D21J Device Identification Block Diagram Pinout SAM D21J QFN64 / TQFP64 UFBGA64 SAM D21G QFN48 / TQFP48 WLCSP45 SAM D21E QFN32 / TQFP32 WLCSP35 Signal Descriptions List I/O Multiplexing and Considerations Multiplexed Signals Other Functions Oscillator Pinout Serial Wire Debug Interface Pinout SERCOM I2C Pins GPIO Clusters TCC Configurations Power Supply and Start-Up Considerations Power Domain Overview Power Supply Considerations Power Supplies Voltage Regulator Typical Powering Schematics Power-Up Sequence Minimum Rise Rate Maximum Rise Rate Power-Up Starting of Clocks I/O Pins Fetching of Initial Instructions Power-On Reset and Brown-Out Detector Power-On Reset on VDDANA Brown-Out Detector on VDDANA Brown-Out Detector on VDDCORE Product Mapping Memories Embedded Memories Physical Memory Map NVM Calibration and Auxiliary Space NVM User Row Mapping NVM Software Calibration Area Mapping Serial Number Processor And Architecture Cortex M0+ Processor Cortex M0+ Configuration Cortex-M0+ Peripherals Cortex-M0+ Address Map I/O Interface Overview Description Nested Vector Interrupt Controller Overview Interrupt Line Mapping Micro Trace Buffer Features Overview High-Speed Bus System Features Configuration SRAM Quality of Service AHB-APB Bridge PAC - Peripheral Access Controller Overview Register Description PAC0 Register Description WPCLR WPSET PAC1 Register Description WPCLR WPSET PAC2 Register Description WPCLR WPSET Peripherals Configuration Summary DSU - Device Service Unit Overview Features Block Diagram Signal Description Product Dependencies IO Lines Power Management Clocks DMA Interrupts Events Register Access Protection Analog Connections Debug Operation Principle of Operation CPU Reset Extension Debugger Probe Detection Cold Plugging Hot Plugging Chip Erase Programming Intellectual Property Protection Device Identification CoreSight Identification Chip Identification Method Functional Description Principle of Operation Basic Operation Initialization Operation From a Debug Adapter Operation From the CPU 32-bit Cyclic Redundancy Check CRC32 Starting CRC32 Calculation Interpreting the Results Debug Communication Channels Testing of On-Board Memories MBIST System Services Availability when Accessed Externally Register Summary Register Description CTRL STATUSA STATUSB ADDR LENGTH DATA DCC0 DCC1 DID ENTRY0 ENTRY1 END MEMTYPE PID4 PID0 PID1 PID2 PID3 CID0 CID1 CID2 CID3 Clock System Clock Distribution Synchronous and Asynchronous Clocks Register Synchronization Common Synchronizer Register Synchronization Overview Write-Synchronization Read-Synchronization Completion of synchronization Read Request Enable Write-Synchronization Software Reset Write-Synchronization Synchronization Delay Distributed Synchronizer Register Synchronization Overview General Write synchronization General read synchronization Completion of synchronization Enable Write-Synchronization Software Reset Write-Synchronization Synchronization Delay Enabling a Peripheral Disabling a Peripheral On-demand, Clock Requests Power Consumption vs. Speed Clocks after Reset GCLK - Generic Clock Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Generic Clock Generator Enabling a Generic Clock Generator Disabling a Generic Clock Generator Selecting a Clock Source for the Generic Clock Generator Changing Clock Frequency Duty Cycle Generic Clock Output on I/O Pins Generic Clock Enabling a Generic Clock Disabling a Generic Clock Selecting a Clock Source for the Generic Clock Configuration Lock Additional Features Indirect Access Generic Clock Enable after Reset Sleep Mode Operation Sleep Walking Run in Standby Mode Synchronization Register Summary Register Description CTRL STATUS CLKCTRL GENCTRL GENDIV PM – Power Manager Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks Main Clock CPU Clock AHB Clock APBx Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Synchronous Clocks Reset Controller Sleep Mode Controller Basic Operation Initialization Enabling, Disabling and Resetting Selecting the Main Clock Source Selecting the Synchronous Clock Division Ratio Clock Ready Flag Peripheral Clock Masking Reset Controller Sleep Mode Controller IDLE Mode STANDBY Mode SleepWalking DMA Operation Interrupts Events Sleep Mode Operation Register Summary Register Description CTRL SLEEP CPUSEL APBASEL APBBSEL APBCSEL AHBMASK APBAMASK APBBMASK APBCMASK INTENCLR INTENSET INTFLAG RCAUSE SYSCTRL – System Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks Interrupts Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation External Multipurpose Crystal Oscillator (XOSC) Operation 32kHz External Crystal Oscillator (XOSC32K) Operation 32kHz Internal Oscillator (OSC32K) Operation 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation 8MHz Internal Oscillator (OSC8M) Operation Digital Frequency Locked Loop (DFLL48M) Operation Basic Operation Open-Loop Operation Closed-Loop Operation Frequency Locking Frequency Error Measurement Drift Compensation Reference Clock Stop Detection Additional Features Dealing with Delay in the DFLL in Closed-Loop Mode USB Clock Recovery Module Wake from Sleep Modes Accuracy FDPLL96M – Fractional Digital Phase-Locked Loop Controller (DFLL96M) Overview Block Diagram Principle of Operation Initialization, Enabling, Disabling and Resetting Reference Clock Switching Loop Divider Ratio updates Digital Filter Selection 3.3V Brown-Out Detector Operation 3.3V Brown-Out Detector (BOD33) Continuous Mode Sampling Mode Hysteresis Voltage Reference System Operation User Control of the Voltage Reference System Voltage Regulator System Operation DMA Operation Interrupts Synchronization Register Summary Register Description INTENCLR INTENSET INTFLAG PCLKSR XOSC XOSC32K OSC32K OSCULP32K OSC8M DFLLCTRL DFLLVAL DFLLMUL DFLLSYNC BOD33 VREG VREF DPLLCTRLA DPLLRATIO DPLLCTRLB DPLLSTATUS WDT – Watchdog Timer Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Configurable Reset Values Enabling and Disabling Normal Mode Window Mode Additional Features Always-On Mode Interrupts Synchronization Register Summary Register Description CTRL CONFIG EWCTRL INTENCLR INTENSET INTFLAG STATUS CLEAR RTC – Real-Time Counter Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Operating Modes 32-Bit Counter (Mode 0) 16-Bit Counter (Mode 1) Clock/Calendar (Mode 2) DMA Operation Interrupts Events Sleep Mode Operation Synchronization Additional Features Periodic Events Frequency Correction Register Summary Register Description CTRL CTRL CTRL READREQ EVCTRL EVCTRL EVCTRL INTENCLR INTENCLR INTENCLR INTENSET INTENSET INTENSET INTFLAG INTFLAG INTFLAG STATUS DBGCTRL FREQCORR COUNT COUNT CLOCK PER COMP COMPn ALARM0 MASK DMAC – Direct Memory Access Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation DMA CRC Basic Operation Initialization Enabling, Disabling, and Resetting Transfer Descriptors Arbitration Data Transmission Transfer Triggers and Actions Addressing Error Handling Additional Features Linked Descriptors Adding Descriptor to the End of a List Modifying a Descriptor in a List Adding a Descriptor Between Existing Descriptors Channel Suspend Channel Resume and Next Suspend Skip Event Input Actions Event Output Selection Aborting Transfers CRC Operation DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRL CRCCTRL CRCDATAIN CRCCHKSUM CRCSTATUS DBGCTRL QOSCTRL SWTRIGCTRL PRICTRL0 INTPEND INTSTATUS BUSYCH PENDCH ACTIVE BASEADDR WRBADDR CHID CHCTRLA CHCTRLB CHINTENCLR CHINTENSET CHINTFLAG CHSTATUS Register Summary - SRAM Register Description - SRAM BTCTRL BTCNT SRCADDR DSTADDR DESCADDR EIC – External Interrupt Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting External Pin Processing Additional Features Non-Maskable Interrupt (NMI) DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRL STATUS NMICTRL NMIFLAG EVCTRL INTENCLR INTENSET INTFLAG WAKEUP CONFIGn NVMCTRL – Non-Volatile Memory Controller Overview Features Block Diagram Signal Description Product Dependencies Power Management Clocks Interrupts Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Initialization Memory Organization Region Lock Bits Command and Data Interface NVM Read RWWEE Read NVM Write Procedure for Manual Page Writes (CTRLB.MANW=1) Procedure for Automatic Page Writes (CTRLB.MANW=0) Page Buffer Clear Erase Row Procedure for Erase Row Lock and Unlock Region Set and Clear Power Reduction Mode NVM User Configuration Security Bit Cache Register Summary Register Description CTRLA CTRLB PARAM INTENCLR INTENSET INTFLAG STATUS ADDR LOCK PORT - I/O Pin Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections CPU Local Bus Functional Description Principle of Operation Basic Operation Initialization Operation I/O Pin Configuration Pin Configurations Summary Input Configuration Totem-Pole Output Digital Functionality Disabled PORT Access Priority Register Summary Register Description DIR DIRCLR DIRSET DIRTGL OUT OUTCLR OUTSET OUTTGL IN CTRL WRCONFIG PMUXn PINCFGn EVSYS – Event System Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting User Multiplexer Setup Channel Setup Channel Path Asynchronous Path Synchronous Path Resynchronized Path Edge Detection Event Generators Channel Status Software Event Interrupts The Overrun Channel n Interrupt The Event Detected Channel n Interrupt Sleep Mode Operation Register Summary Register Description CTRL CHANNEL USER CHSTATUS INTENCLR INTENSET INTFLAG SERCOM – Serial Communication Interface Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Clock Generation – Baud-Rate Generator Asynchronous Arithmetic Mode BAUD Value Selection Additional Features Address Match and Mask Address With Mask Two Unique Addresses Address Range DMA Operation Interrupts Events Sleep Mode Operation Synchronization SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter Overview USART Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Clock Generation and Selection Synchronous Clock Operation Data Register Data Transmission Disabling the Transmitter Data Reception Disabling the Receiver Error Bits Asynchronous Data Reception Asynchronous Operational Range Additional Features Parity Hardware Handshaking IrDA Modulation and Demodulation Break Character Detection and Auto-Baud Collision Detection Loop-Back Mode Start-of-Frame Detection Sample Adjustment DMA, Interrupts and Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLB BAUD RXPL INTENCLR INTENSET INTFLAG STATUS SYNCBUSY DATA DBGCTRL SERCOM SPI – SERCOM Serial Peripheral Interface Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Clock Generation Data Register SPI Transfer Modes Transferring Data Master Slave Receiver Error Bit Additional Features Address Recognition Preloading of the Slave Shift Register Master with Several Slaves Loop-Back Mode Hardware Controlled SS Slave Select Low Detection DMA, Interrupts, and Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLB BAUD INTENCLR INTENSET INTFLAG STATUS SYNCBUSY ADDR DATA DBGCTRL SERCOM I2C – SERCOM Inter-Integrated Circuit Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting I2C Bus State Logic I2C Master Operation Master Clock Generation Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus) Master Clock Generation (High-Speed Mode) Transmitting Address Packets Transmitting Data Packets Receiving Data Packets (SCLSM=0) Receiving Data Packets (SCLSM=1) High-Speed Mode 10-Bit Addressing I2C Slave Operation Receiving Address Packets (SCLSM=0) Receiving Address Packets (SCLSM=1) Receiving and Transmitting Data Packets High-Speed Mode 10-Bit Addressing PMBus Group Command Additional Features SMBus Smart Mode 4-Wire Mode Quick Command DMA, Interrupts and Events DMA Operation Slave DMA Master DMA Interrupts Events Sleep Mode Operation Synchronization Register Summary - I2C Slave Register Description - I2C Slave CTRLA CTRLB INTENCLR INTENSET INTFLAG STATUS SYNCBUSY ADDR DATA Register Summary - I2C Master Register Description - I2C Master CTRLA CTRLB BAUD INTENCLR INTENSET INTFLAG STATUS SYNCBUSY ADDR DATA DBGCTRL I2S - Inter-IC Sound Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Initialization Basic Operation Master Clock, Serial Clock, and Frame Sync Generation Slave Mode Master Mode and Controller Mode MCKn Clock Frequency SCKn Clock Frequency Relation Between MCKn, SCKn, and Sampling Frequency fs Data Holding Registers Data Reception Mode Data Transmission Mode Master, Controller, and Slave Modes I2S Format - Reception and Transmission Sequence with Word Select TDM Format - Reception and Transmission Sequence PDM Reception Data Formatting Unit DMA, Interrupts and Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Loop-Back Mode I2S Application Examples Register Summary Register Description CTRLA CLKCTRLn INTENCLR INTENSET INTFLAG SYNCBUSY SERCTRLn DATAmn RXDATA TC – Timer/Counter Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Prescaler Selection Counter Mode Counter Operations Stop Command and Event Action Re-Trigger Command and Event Action Count Event Action Start Event Action Compare Operations Waveform Output Operations Frequency Operation PWM Operation Changing the Top Value Capture Operations Event Capture Action Period and Pulse-Width (PPW) Capture Action Additional Features One-Shot Operation DMA, Interrupts and Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA READREQ CTRLBCLR CTRLBSET CTRLC DBGCTRL EVCTRL INTENCLR INTENSET INTFLAG STATUS Counter Value COUNT COUNT COUNT Period Value PER Compare/Capture CCx CCx CCx TCC – Timer/Counter for Control Applications Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling, and Resetting Prescaler Selection Counter Operation Compare Operations Waveform Output Generation Operations Normal Frequency (NFRQ) Match Frequency (MFRQ) Normal Pulse-Width Modulation (NPWM) Single-Slope PWM Operation Dual-Slope PWM Generation Dual-Slope Critical PWM Generation Output Polarity Double Buffering Capture Operations Additional Features One-Shot Operation Circular Buffer Dithering Operation Ramp Operations Recoverable Faults Non-Recoverable Faults Waveform Extension WaveformGenerationinRAMP1modeWithRestartAction DMA, Interrupts, and Events DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA CTRLBCLR CTRLBSET SYNCBUSY FCTRLA, FCTRLB WEXCTRL DRVCTRL DBGCTRL EVCTRL INTENCLR INTENSET INTFLAG STATUS COUNT PATT WAVE PER CCn PATTB WAVEB PERB CCBn USB – Universal Serial Bus Overview Features USB Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Calibration Functional Description USB General Operation Initialization USB Device Operations Initialization Endpoint Configuration Multi-Packet Transfers USB Reset Start-of-Frame Management of SETUP Transactions Management of OUT Transactions Multi-Packet Transfers for OUT Endpoint Management of IN Transactions Multi-Packet Transfers for IN Endpoint Ping-Pong Operation Feedback Operation Suspend State and Pad Behavior Remote Wakeup Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device USB Device Interrupt Host Operations Device Detection and Disconnection Host Terminology USB Reset Pipe Configuration Pipe Activation Pipe Address Setup Suspend and Wakeup Phase-locked SOFs Management of Control Pipes Management of IN Pipes Management of OUT Pipes Alternate Pipe Data Flow Error CRC Error PERR Error Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host. Host Interrupt Register Summary Common Device Summary Device Summary Host Summary Register Description Communication Device Host Registers CTRLA SYNCBUSY QOSCTRL FSMSTATUS DESCADD PADCAL Device Registers - Common CTRLB DADD STATUS FNUM INTENCLR INTENSET INTFLAG EPINTSMRY Device Registers - Endpoint EPCFGn EPSTATUSCLRn EPSTATUSSETn EPSTATUSn EPINTFLAGn EPINTENCLRn EPINTENSETn Device Registers - Endpoint RAM Endpoint Descriptor Structure ADDR PCKSIZE EXTREG STATUS_BK Host Registers - Common CTRLB HSOFC STATUS FNUM FLENHIGH INTENCLR INTENSET INTFLAG PINTSMRY Host Registers - Pipe PCFGn BINTERVAL PSTATUSCLR PSTATUSSET PSTATUS PINTFLAG PINTENCLR PINTENSET Host Registers - Pipe RAM Pipe Descriptor Structure ADDR PCKSIZE EXTREG STATUS_BK CTRL_PIPE STATUS_PIPE ADC – Analog-to-Digital Converter Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Calibration Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Reset Operation Prescaler ADC Resolution Differential and Single-Ended Conversions Conversion Timing Accumulation Averaging Oversampling and Decimation Window Monitor Offset and Gain Correction DMA Operation Interrupts Events Sleep Mode Operation Synchronization Register Summary Register Description CTRLA REFCTRL AVGCTRL SAMPCTRL CTRLB WINCTRL SWTRIG INPUTCTRL EVCTRL INTENCLR INTENSET INTFLAG STATUS RESULT WINLT WINUT GAINCORR OFFSETCORR CALIB DBGCTRL AC – Analog Comparators Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Comparator Configuration Starting a Comparison Continuous Measurement Single-Shot Selecting Comparator Inputs Window Operation Voltage Doubler VDDANA Scaler Input Hysteresis Propagation Delay vs. Power Consumption Filtering Comparator Output Offset Compensation Interrupts Events Sleep Mode Operation Continuous Measurement during Sleep Single-Shot Measurement during Sleep Synchronization Register Summary Register Description CTRLA CTRLB EVCTRL INTENCLR INTENSET INTFLAG STATUSA STATUSB STATUSC WINCTRL COMPCTRL0, COMPCTRL1 SCALERn DAC – Digital-to-Analog Converter Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Power Management Clocks DMA Interrupts Events Debug Operation Register Access Protection Analog Connections Functional Description Principle of Operation Basic Operation Initialization Enabling, Disabling and Resetting Enabling the Output Buffer Digital to Analog Conversion DMA Operation Interrupts Events Sleep Mode Operation Synchronization Additional Features DAC as an Internal Reference Data Buffer Voltage Pump Register Summary Register Description CTRLA CTRLB EVCTRL INTENCLR INTENSET INTFLAG STATUS DATA DATABUF PTC - Peripheral Touch Controller Overview Features Block Diagram Signal Description Product Dependencies I/O Lines Mutual-capacitance Sensor Arrangement Self-capacitance Sensor Arrangement Clocks Functional Description Electrical Characteristics Disclaimer Absolute Maximum Ratings General Operating Ratings Supply Characteristics Maximum Clock Frequencies Power Consumption Peripheral Power Consumption All peripheral except USB USB Peripheral Power Consumption I/O Pin Characteristics Normal I/O Pins I2C Pins XOSC Pin XOSC32 Pin External Reset Pin Injection Current Analog Characteristics Voltage Regulator Characteristics Power-On Reset (POR) Characteristics Brown-Out Detectors Characteristics BOD33 Analog-to-Digital (ADC) characteristics Performance with the Averaging Digital Feature Performance with the hardware offset and gain correction Inputs and Sample and Hold Acquisition Times Digital to Analog Converter (DAC) Characteristics Analog Comparator Characteristics Internal 1.1V Bandgap Reference Characteristics Temperature Sensor Characteristics Temperature Sensor Characteristics Software-based Refinement of the Actual Temperature Temperature Log Row Using Linear Interpolation NVM Characteristics Oscillators Characteristics Crystal Oscillator (XOSC) Characteristics Digital Clock Characteristics Crystal Oscillator Characteristics External 32 kHz Crystal Oscillator (XOSC32K) Characteristics Digital Clock Characteristics Crystal Oscillator Characteristics Digital Frequency Locked Loop (DFLL48M) Characteristics 32.768kHz Internal oscillator (OSC32K) Characteristics Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics 8MHz RC Oscillator (OSC8M) Characteristics Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics PTC Typical Characteristics Device Variant A Device Variant B USB Characteristics Timing Characteristics External Reset SERCOM in SPI Mode Timing SERCOM in I2C Mode Timing SWD Timing I2S Timing Packaging Information Thermal Considerations Thermal Resistance Data Junction Temperature Package Drawings 64 pin TQFP 64 pin QFN 64-ball UFBGA 48 pin TQFP 48 pin QFN 45-ball WLCSP 32 pin TQFP 32 pin QFN 35 ball WLCSP (Device Variant B) Soldering Profile Schematic Checklist Introduction Operation in Noisy Environment Power Supply Power Supply Connections External Analog Reference Connections External Reset Circuit Clocks and Crystal Oscillators External Clock Source Crystal Oscillator External Real Time Oscillator Calculating the Correct Crystal Decoupling Capacitor Unused or Unconnected Pins Programming and Debug Ports Cortex Debug Connector (10-pin) 10-pin JTAGICE3 Compatible Serial Wire Debug Interface 20-pin IDC JTAG Connector USB Interface Errata Device Variant A Device Variant B Conventions Numerical Notation Memory Size and Type Frequency and Time Registers and Bits Acronyms and Abbreviations Datasheet Revision History Rev. N – 10/2016 Rev. M – 09/2016 Rev. L – 09/2016 Rev. K – 09/2016 Rev. J – 07/2016 Rev. I – 03/2016 Rev. H – 01/2016 Rev. G – 09/2015 Rev. F – 07/2015 Rev. E – 02/2015 Rev. D – 09/2014 Rev. C – 07/2014 Rev. B – 07/2014 Rev. A - 02/2014 Appendix A. Electrical Characteristics at 125°C Disclaimer Absolute Maximum Ratings General Operating Ratings Maximum Clock Frequencies Power Consumption Analog Characteristics Power-On Reset (POR) Characteristics Brown-Out Detectors Characteristics BOD33 Analog-to-Digital (ADC) characteristics Inputs and Sample and Hold Acquisition Times Digital to Analog Converter (DAC) Characteristics Analog Comparator Characteristics Temperature Sensor Characteristics NVM Characteristics Oscillators Characteristics Crystal Oscillator (XOSC) Characteristics Digital Clock Characteristics Crystal Oscillator Characteristics External 32 kHz Crystal Oscillator (XOSC32K) Characteristics Digital Clock Characteristics Crystal Oscillator Characteristics Digital Frequency Locked Loop (DFLL48M) Characteristics 32.768kHz Internal oscillator (OSC32K) Characteristics Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics 8MHz RC Oscillator (OSC8M) Characteristics Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics USB Characteristics Timing Characteristics SERCOM in SPI Mode Timing SERCOM in I2C Mode Timing I2S Timing Legal Disclaimer