There are four combinations of SCK phase and polarity with respect to serial data. Table 1 shows the clock polarity (CPOL) and clock phase (CPHA) in the different modes. Leading edge is the first clock edge in a clock cycle and trailing edge is the last clock edge in a clock cycle.
Mode |
CPOL |
CPHA |
Leading Edge |
Trailing Edge |
|---|---|---|---|---|
0 |
0 |
0 |
Rising, Sample |
Falling, Setup |
1 |
0 |
1 |
Rising, Setup |
Falling, Sample |
2 |
1 |
0 |
Falling, Sample |
Rising, Setup |
3 |
1 |
1 |
Falling, Setup |
Rising, Sample |