Split Mode - Two 8-Bit Timer/Counters

Split Mode Overview

To double the number of timers and PWM channels in the TCA, a Split mode is provided. In this Split mode, the 16-bit timer/counter acts as two separate 8-bit timers, which each have three compare channels for PWM generation. The Split mode will only work with single-slope down-count. Event controlled operation is not supported in Split mode.

Activating Split mode results in changes to the functionality of some registers and register bits. The modifications are described in a separate register map (see Register Summary - TCAn in Split Mode).

Split Mode Differences Compared to Normal Mode

Count:
- Down-count only
- Low Byte Timer Counter Register (TCAn.LCNT) and High Byte Timer Counter Register (TCAn.HCNT) are independent
Waveform Generation:
- Single-slope PWM only (WGMODE = SINGLESLOPE in TCAn.CTRLB)
Interrupt:
- No change for Low Byte Timer Counter Register (TCAn.LCNT)
- Underflow interrupt for High Byte Timer Counter Register (TCAn.HCNT)
- No compare interrupt or flag for High Byte Compare Register n (TCAn.HCMPn)
Event Actions: Not Compatible
Buffer Registers and Buffer Valid Flags: Unused
Register Access: Byte Access to All Registers

Block Diagram

Figure 1. Timer/Counter Block Diagram Split Mode

Split Mode Initialization

When shifting between Normal mode and Split mode, the functionality of some registers and bits changes, but their values do not. For this reason, disabling the peripheral (ENABLE = 0 in TCAn.CTRLA) and doing a hard Reset (CMD = RESET in TCAn.CTRLESET) is recommended when changing the mode to avoid unexpected behavior.

To start using the timer/counter in basic Split mode after a hard Reset, follow these steps:

1.Enable Split mode by writing a ‘1’ to the Split mode enable bit in the Control D register (SPLITM in TCAn.CTRLD).
2.Write a TOP value to the Period registers (TCAn.PER).
3.Enable the peripheral by writing a ‘1’ to the ENABLE bit in the Control A register (TCAn.CTRLA).
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bit field (CLKSEL) in TCAn.CTRLA.
4.The counter values can be read from the Counter bit field in the Counter registers (TCAn.CNT).