Any programming or debug session should be terminated by writing the UPDI
Disable (UPDIDIS) bit in UPDI.CTRLB. Writing this bit will reset the UPDI including any
decoded KEYs (see the KEY instruction section) and disable the
oscillator request for the module. If the disable operation is not performed, the UPDI
and the oscillators request will remain enabled. This causes power consumption increased
for the application.
During the enable sequence the UPDI can disable itself in case of a faulty
enable sequence. There are two cases that will cause an automatic disable:
- A SYNCH character is not sent
within 13.5 ms after the initial enable pulse described in UPDI Enable.
- The first SYNCH character after
an initiated enable is too short or too long to be detected as a valid SYNCH
character. See Table 1 for recommended baud rate operating
ranges.