| Generator Name | Description | Event Type | Generating Clock Domain | Length of Event | |
|---|---|---|---|---|---|
| Peripheral | Event | ||||
| TCAn | OVF_LUNF |
Normal mode: Overflow Split mode: Low byte timer underflow |
Pulse | CLK_PER | One CLK_PER period |
| HUNF |
Normal mode: Not available Split mode: High byte timer underflow |
Pulse | CLK_PER | One CLK_PER period | |
| CMP0 |
Normal mode: Compare Channel 0 match Split mode: Low byte timer Compare Channel 0 match |
Pulse | CLK_PER | One CLK_PER period | |
| CMP1 |
Normal mode: Compare Channel 1 match Split mode: Low byte timer Compare Channel 1 match |
Pulse | CLK_PER | One CLK_PER period | |
| CMP2 |
Normal mode: Compare Channel 2 match Split mode: Low byte timer Compare Channel 2 match |
Pulse | CLK_PER | One CLK_PER period | |
| User Name | Description | Input Detection | Async/Sync |
|---|---|---|---|
| TCAn | Count on positive event edge | Edge | Sync |
| Count on any event edge | Edge | Sync | |
| Count while event signal is high | Level | Sync | |
| Event level controls count direction, up when low and down when high | Level | Sync |
The specific actions described in the table above are selected by writing to
the Event Action bits (EVACT) in the Event Control register (TCAn.EVCTRL). Input events are
enabled by writing a ‘1’ to the Enable Count on Event Input bit (CNTEI in
TCAn.EVCTRL).
Event inputs are not used in Split mode.
Refer to the Event System (EVSYS) chapter for more details regarding event types and Event System configuration.