SS Pin Functionality in Master Mode - Multi-Master Support

In Master mode, the Slave Select Disable bit in Control Register B (SSD bit in SPIn.CTRLB) controls how the SPI uses the SS line.

If SSD in SPIn.CTRLB is ‘0’ and the SS is configured as an output pin, it can be used as a regular I/O pin or by other peripheral modules, and will not affect the SPI system.

If the SSD bit in SPIn.CTRLB is ‘0’ and the SS is configured as an input pin, the SS pin must be held high to ensure master SPI operation. A low level will be interpreted as another master is trying to take control of the bus. This will switch the SPI into Slave mode and the hardware of the SPI will perform the following actions:
  1. 1.The master bit in the SPI Control A Register (MASTER in SPIn.CTRLA) is cleared and the SPI system becomes a slave. The direction of the pins will be switched according to Table 1.
  2. 2.The interrupt flag in the Interrupt Flags register (IF in SPIn.INTFLAGS) will be set. If the interrupt is enabled and the global interrupts are enabled the interrupt routine will be executed.
Table 1. Overview of the SS Pin Functionality when the SSD Bit in SPIn.CTRLB is Zero
SS Configuration SS Pin-Level Description
Input High Master activated (selected)
Low Master deactivated, switched to Slave mode
Output High Master activated (selected)
Low
Note:

If the AVR device is configured for Master mode and it cannot be ensured that the SS pin will stay high between two transmissions, the status of the Master bit (the MASTER bit in SPIn.CTRLA) has to be checked before a new byte is written. After the Master bit has been cleared by a low level on the SS line, it must be set by the application to re-enable the SPI Master mode.

Parent topic: Master Mode Operation