Contents

Introduction megaAVR 0-series Overview 1.1. Memory Overview 1.2. Peripheral Overview Features 1. Silicon Errata and Data Sheet Clarification Document 2. Block Diagram 3. Pinout 3.1. 28-Pin SSOP 3.2. 32-Pin VQFN/TQFP 3.3. 48-Pin UQFN/TQFP 4. I/O Multiplexing and Considerations 4.1. Multiplexed Signals 5. Conventions 5.1. Numerical Notation 5.2. Memory Size and Type 5.3. Frequency and Time 5.4. Registers and Bits 5.4.1. Addressing Registers from Header Files 5.5. ADC Parameter Definitions 6. AVR CPU 6.1. Features 6.2. Overview 6.3. Architecture 6.4. Arithmetic Logic Unit (ALU) 6.4.1. Hardware Multiplier 6.5. Functional Description 6.5.1. Program Flow 6.5.2. Instruction Execution Timing 6.5.3. Status Register 6.5.4. Stack and Stack Pointer 6.5.5. Register File 6.5.5.1. The X-, Y-, and Z-Registers 6.5.6. Accessing 16-Bit Registers 6.5.7. Configuration Change Protection (CCP) 6.5.7.1. Sequence for Write Operation to Configuration Change Protected I/O Registers 6.5.7.2. Sequence for Execution of Self-Programming 6.5.8. On Chip Debug Capabilities 6.6. Register Summary - CPU 6.7. Register Description 6.7.1. CCP 6.7.2. SP 6.7.3. SREG 7. Memories 7.1. Overview 7.2. Memory Map 7.3. In-System Reprogrammable Flash Program Memory 7.4. SRAM Data Memory 7.5. EEPROM Data Memory 7.6. User Row (USERROW) 7.7. Signature Row (SIGROW) 7.7.1. Signature Row Summary 7.7.2. Signature Row Description 7.7.2.1. Device ID n 7.7.2.2. Serial Number Byte n 7.7.2.3. OSC16 Calibration byte 7.7.2.4. OSC16 Temperature Calibration byte 7.7.2.5. OSC20 Calibration byte 7.7.2.6. OSC20 Temperature Calibration byte 7.7.2.7. Temperature Sensor Calibration n 7.7.2.8. OSC16 Error at 3V 7.7.2.9. OSC16 Error at 5V 7.7.2.10. OSC20 Error at 3V 7.7.2.11. OSC20 Error at 5V 7.8. Fuses (FUSE) 7.8.1. Fuse Summary - FUSE 7.8.2. Fuse Description 7.8.2.1. Watchdog Configuration 7.8.2.2. BOD Configuration 7.8.2.3. Oscillator Configuration 7.8.2.4. System Configuration 0 7.8.2.5. System Configuration 1 7.8.2.6. Application Code End 7.8.2.7. Boot End 7.8.2.8. Lockbits 7.9. Memory Section Access from CPU and UPDI on Locked Device 7.10. I/O Memory 7.10.1. Register Summary 7.10.2. Register Description 7.10.2.1. General Purpose I/O Register n 8. Peripherals and Architecture 8.1. Peripheral Module Address Map 8.2. Interrupt Vector Mapping 8.3. System Configuration (SYSCFG) 8.3.1. Register Summary 8.3.2. Register Description - SYSCFG 8.3.2.1. Device Revision ID Register 9. NVMCTRL - Nonvolatile Memory Controller 9.1. Features 9.2. Overview 9.2.1. Block Diagram 9.3. Functional Description 9.3.1. Memory Organization 9.3.1.1. Flash 9.3.1.2. EEPROM 9.3.1.3. User Row 9.3.2. Memory Access 9.3.2.1. Read 9.3.2.2. Page Buffer Load 9.3.2.3. Programming 9.3.2.4. Commands 9.3.2.4.1. Write Command 9.3.2.4.2. Erase Command 9.3.2.4.3. Erase-Write Operation 9.3.2.4.4. Page Buffer Clear Command 9.3.2.4.5. Chip Erase Command 9.3.2.4.6. EEPROM Erase Command 9.3.2.4.7. Fuse Write Command 9.3.3. Preventing Flash/EEPROM Corruption 9.3.4. Interrupts 9.3.5. Sleep Mode Operation 9.3.6. Configuration Change Protection 9.4. Register Summary - NVMCTRL 9.5. Register Description 9.5.1. Control A 9.5.2. Control B 9.5.3. Status 9.5.4. Interrupt Control 9.5.5. Interrupt Flags 9.5.6. Data 9.5.7. Address 10. CLKCTRL - Clock Controller 10.1. Features 10.2. Overview 10.2.1. Block Diagram - CLKCTRL 10.2.1.1. 9e1c050cc8db10bfa8b0b43c32b46fa62ecaae9c.png 10.2.2. Signal Description 10.3. Functional Description 10.3.1. Sleep Mode Operation 10.3.2. Main Clock Selection and Prescaler 10.3.3. Main Clock After Reset 10.3.4. Clock Sources 10.3.4.1. Internal Oscillators 10.3.4.1.1. 16/20 MHz Oscillator (OSC20M) 10.3.4.1.1.1. OSC20M Stored Frequency Error Compensation 10.3.4.1.2. 32 KHz Oscillator (OSCULP32K) 10.3.4.2. External Clock Sources 10.3.4.2.1. 32.768 kHz Crystal Oscillator (XOSC32K) 10.3.4.2.2. External Clock (EXTCLK) 10.3.5. Configuration Change Protection 10.4. Register Summary - CLKCTRL 10.5. Register Description 10.5.1. Main Clock Control A 10.5.2. Main Clock Control B 10.5.3. Main Clock Lock 10.5.4. Main Clock Status 10.5.5. 16/20 MHz Oscillator Control A 10.5.6. 16/20 MHz Oscillator Calibration A 10.5.7. 16/20 MHz Oscillator Calibration B 10.5.8. 32 KHz Oscillator Control A 10.5.9. 32.768 kHz Crystal Oscillator Control A 11. SLPCTRL - Sleep Controller 11.1. Features 11.2. Overview 11.2.1. Block Diagram 11.3. Functional Description 11.3.1. Initialization 11.3.2. Operation 11.3.2.1. Sleep Modes 11.3.2.2. Wake-Up Time 11.3.3. Debug Operation 11.4. Register Summary - SLPCTRL 11.5. Register Description 11.5.1. Control A 12. RSTCTRL - Reset Controller 12.1. Features 12.2. Overview 12.2.1. Block Diagram 12.2.2. Signal Description 12.3. Functional Description 12.3.1. Initialization 12.3.2. Operation 12.3.2.1. Reset Sources 12.3.2.1.1. Power-On Reset (POR) 12.3.2.1.2. Brown-Out Detector (BOD) Reset 12.3.2.1.3. Software Reset 12.3.2.1.4. External Reset 12.3.2.1.5. Watchdog Reset 12.3.2.1.6. Universal Program Debug Interface (UPDI) Reset 12.3.2.1.7. Domains Affected By Reset 12.3.2.2. Reset Time 12.3.3. Sleep Mode Operation 12.3.4. Configuration Change Protection 12.4. Register Summary - RSTCTRL 12.5. Register Description 12.5.1. Reset Flag Register 12.5.2. Software Reset Register 13. CPUINT - CPU Interrupt Controller 13.1. Features 13.2. Overview 13.2.1. Block Diagram 13.3. Functional Description 13.3.1. Initialization 13.3.2. Operation 13.3.2.1. Enabling, Disabling, and Resetting 13.3.2.2. Interrupt Vector Locations 13.3.2.3. Interrupt Response Time 13.3.2.4. Interrupt Priority 13.3.2.4.1. Non-Maskable Interrupts (NMI) 13.3.2.4.2. High Priority Interrupt 13.3.2.4.3. Normal Priority Interrupts 13.3.2.4.3.1. Scheduling of Normal Priority Interrupts 13.3.2.4.3.1.1. Static Scheduling 13.3.2.4.3.1.2. Round Robin Scheduling 13.3.2.5. Compact Vector Table 13.3.3. Configuration Change Protection 13.4. Register Summary - CPUINT 13.5. Register Description 13.5.1. Control A 13.5.2. Status 13.5.3. Interrupt Priority Level 0 13.5.4. Interrupt Vector with Priority Level 1 14. EVSYS - Event System 14.1. Features 14.2. Overview 14.2.1. Block Diagram 14.2.2. Signal Description 14.3. Functional Description 14.3.1. Initialization 14.3.2. Operation 14.3.2.1. Event User Multiplexer Setup 14.3.2.2. Event System Channel 14.3.2.3. Event Generators 14.3.2.4. Event Users 14.3.2.5. Synchronization 14.3.2.6. Software Event 14.3.3. Sleep Mode Operation 14.3.4. Debug Operation 14.4. Register Summary - EVSYS 14.5. Register Description 14.5.1. Channel Strobe 14.5.2. Channel n Generator Selection 14.5.3. User Channel Mux 15. PORTMUX - Port Multiplexer 15.1. Overview 15.2. Register Summary - PORTMUX 15.3. Register Description 15.3.1. PORTMUX Control for Event System 15.3.2. PORTMUX Control for CCL 15.3.3. PORTMUX Control for USART 15.3.4. PORTMUX Control for TWI and SPI 15.3.5. PORTMUX Control for TCA 15.3.6. PORTMUX Control for TCB 16. PORT - I/O Pin Configuration 16.1. Features 16.2. Overview 16.2.1. Block Diagram 16.2.2. Signal Description 16.3. Functional Description 16.3.1. Initialization 16.3.2. Operation 16.3.2.1. Basic Functions 16.3.2.2. Pin Configuration 16.3.2.3. Virtual Ports 16.3.2.4. Peripheral Override 16.3.3. Interrupts 16.3.4. Events 16.3.5. Sleep Mode Operation 16.4. Register Summary - PORTx 16.5. Register Description - Ports 16.5.1. Data Direction 16.5.2. Data Direction Set 16.5.3. Data Direction Clear 16.5.4. Data Direction Toggle 16.5.5. Output Value 16.5.6. Output Value Set 16.5.7. Output Value Clear 16.5.8. Output Value Toggle 16.5.9. Input Value 16.5.10. Interrupt Flags 16.5.11. Pin n Control 16.6. Register Summary - VPORTx 16.7. Register Description - Virtual Ports 16.7.1. Data Direction 16.7.2. Output Value 16.7.3. Input Value 16.7.4. Interrupt Flag 17. BOD - Brown-out Detector 17.1. Features 17.2. Overview 17.2.1. Block Diagram 17.3. Functional Description 17.3.1. Initialization 17.3.2. Interrupts 17.3.3. Sleep Mode Operation 17.3.4. Configuration Change Protection 17.4. Register Summary - BOD 17.5. Register Description 17.5.1. Control A 17.5.2. Control B 17.5.3. VLM Control A 17.5.4. Interrupt Control 17.5.5. VLM Interrupt Flags 17.5.6. VLM Status 18. VREF - Voltage Reference 18.1. Features 18.2. Overview 18.2.1. Block Diagram 18.3. Functional Description 18.3.1. Initialization 18.4. Register Summary - VREF 18.5. Register Description 18.5.1. Control A 18.5.2. Control B 19. WDT - Watchdog Timer 19.1. Features 19.2. Overview 19.2.1. Block Diagram 19.2.2. Signal Description 19.3. Functional Description 19.3.1. Initialization 19.3.2. Clocks 19.3.3. Operation 19.3.3.1. Normal Mode 19.3.3.2. Window Mode 19.3.3.3. Configuration Protection and Lock 19.3.4. Sleep Mode Operation 19.3.5. Debug Operation 19.3.6. Synchronization 19.3.7. Configuration Change Protection 19.4. Register Summary - WDT 19.5. Register Description 19.5.1. Control A 19.5.2. Status 20. TC0/1 – 16-bit Timer/Counter Type 0 and 1 20.1. Features 20.2. Overview 20.2.1. Block Diagram 20.2.2. Signal Description 20.3. Functional Description 20.3.1. Definitions 20.3.2. Initialization 20.3.3. Operation 20.3.3.1. Normal Operation 20.3.3.2. Double Buffering 20.3.3.3. Changing the Period 20.3.3.4. Compare Channel 20.3.3.4.1. Waveform Generation 20.3.3.4.2. Frequency (FRQ) Waveform Generation 20.3.3.4.3. Single-Slope PWM Generation 20.3.3.4.4. Dual-Slope PWM 20.3.3.4.5. Port Override for Waveform Generation 20.3.3.5. Timer/Counter Commands 20.3.3.6. Split Mode - Two 8-Bit Timer/Counters 20.3.4. Events 20.3.5. Interrupts 20.3.6. Sleep Mode Operation 20.4. Register Summary - TCAn in Normal Mode 20.5. Register Description - Normal Mode 20.5.1. Control A 20.5.2. Control B - Normal Mode 20.5.3. Control C - Normal Mode 20.5.4. Control D 20.5.5. Control Register E Clear - Normal Mode 20.5.6. Control Register E Set - Normal Mode 20.5.7. Control Register F Clear 20.5.8. Control Register F Set 20.5.9. Event Control 20.5.10. Interrupt Control Register - Normal Mode 20.5.11. Interrupt Flag Register - Normal Mode 20.5.12. Debug Control Register 20.5.13. Temporary Bits for 16-Bit Access 20.5.14. Counter Register - Normal Mode 20.5.15. Period Register - Normal Mode 20.5.16. Compare n Register - Normal Mode 20.5.17. Period Buffer Register 20.5.18. Period Buffer Register High 20.5.19. Compare n Buffer Register 20.6. Register Summary - TCAn in Split Mode 20.7. Register Description - Split Mode 20.7.1. Control A 20.7.2. Control B - Split Mode 20.7.3. Control C - Split Mode 20.7.4. Control D 20.7.5. Control Register E Clear - Split Mode 20.7.6. Control Register E Set - Split Mode 20.7.7. Interrupt Control Register - Split Mode 20.7.8. Interrupt Flag Register - Split Mode 20.7.9. Debug Control Register 20.7.10. Low Byte Timer Counter Register - Split Mode 20.7.11. High Byte Timer Counter Register - Split Mode 20.7.12. Low Byte Timer Period Register - Split Mode 20.7.13. High Byte Period Register - Split Mode 20.7.14. Compare Register n For Low Byte Timer - Split Mode 20.7.15. High Byte Compare Register n - Split Mode 21. TCB - 16-bit Timer/Counter Type B 21.1. Features 21.2. Overview 21.2.1. Block Diagram 21.2.2. Signal Description 21.3. Functional Description 21.3.1. Definitions 21.3.2. Initialization 21.3.3. Operation 21.3.3.1. Modes 21.3.3.1.1. Periodic Interrupt Mode 21.3.3.1.2. Time-Out Check Mode 21.3.3.1.3. Input Capture on Event Mode 21.3.3.1.4. Input Capture Frequency Measurement Mode 21.3.3.1.5. Input Capture Pulse-Width Measurement Mode 21.3.3.1.6. Input Capture Frequency and Pulse-Width Measurement Mode 21.3.3.1.7. Single-Shot Mode 21.3.3.1.8. 8-Bit PWM Mode 21.3.3.2. Output 21.3.3.3. Noise Canceler 21.3.3.4. Synchronized with Timer/Counter Type A 21.3.4. Events 21.3.5. Interrupts 21.3.6. Sleep Mode Operation 21.4. Register Summary - TCB 21.5. Register Description 21.5.1. Control A 21.5.2. Control B 21.5.3. Event Control 21.5.4. Interrupt Control 21.5.5. Interrupt Flags 21.5.6. Status 21.5.7. Debug Control 21.5.8. Temporary Value 21.5.9. Count 21.5.10. Capture/Compare 22. RTC - Real-Time Counter 22.1. Features 22.2. Overview 22.2.1. Block Diagram 22.3. Clocks 22.4. RTC Functional Description 22.4.1. Initialization 22.4.1.1. Configure the Clock CLK_RTC 22.4.1.2. Configure RTC 22.4.2. Operation - RTC 22.4.2.1. Enabling, Disabling, and Resetting 22.5. PIT Functional Description 22.5.1. Initialization 22.5.2. Operation - PIT 22.5.2.1. Enabling, Disabling, and Resetting 22.5.2.2. PIT Interrupt Timing 22.6. Crystal Error Correction 22.7. Events 22.8. Interrupts 22.9. Sleep Mode Operation 22.10. Synchronization 22.11. Debug Operation 22.12. Register Summary - RTC 22.13. Register Description 22.13.1. Control A 22.13.2. Status 22.13.3. Interrupt Control 22.13.4. Interrupt Flag 22.13.5. Temporary 22.13.6. Debug Control 22.13.7. Crystal Frequency Calibration 22.13.8. Clock Selection 22.13.9. Count 22.13.10. Period 22.13.11. Compare 22.13.12. Periodic Interrupt Timer Control A 22.13.13. Periodic Interrupt Timer Status 22.13.14. PIT Interrupt Control 22.13.15. PIT Interrupt Flag 22.13.16. Periodic Interrupt Timer Debug Control 23. USART - Universal Synchronous and Asynchronous Receiver and Transmitter 23.1. Features 23.2. Overview 23.2.1. Block Diagram 23.2.2. Signal Description 23.3. Functional Description 23.3.1. Initialization 23.3.2. Operation 23.3.2.1. Frame Formats 23.3.2.2. Clock Generation 23.3.2.2.1. The Fractional Baud Rate Generator 23.3.2.3. Data Transmission 23.3.2.3.1. Disabling the Transmitter 23.3.2.4. Data Reception 23.3.2.4.1. Receiver Error Flags 23.3.2.4.2. Disabling the Receiver 23.3.2.4.3. Flushing the Receive Buffer 23.3.3. Communication Modes 23.3.3.1. Synchronous Operation 23.3.3.1.1. Clock Operation 23.3.3.1.2. External Clock Limitations 23.3.3.1.3. USART in Master SPI Mode 23.3.3.1.3.1. Frame Formats 23.3.3.1.3.2. Clock Generation 23.3.3.1.3.3. Data Transmission 23.3.3.1.3.4. Data Reception 23.3.3.1.3.5. USART in Master SPI Mode vs. SPI 23.3.3.2. Asynchronous Operation 23.3.3.2.1. Clock Recovery 23.3.3.2.2. Data Recovery 23.3.3.2.3. Error Tolerance 23.3.3.2.4. Double-Speed Operation 23.3.3.2.5. Auto-Baud 23.3.3.2.6. Half Duplex Operation 23.3.3.2.6.1. One-Wire Mode 23.3.3.2.6.2. RS-485 Mode 23.3.3.2.7. IRCOM Mode of Operation 23.3.4. Additional Features 23.3.4.1. Parity 23.3.4.2. Start-of-Frame Detection 23.3.4.3. Multiprocessor Communication 23.3.4.3.1. Using Multiprocessor Communication 23.3.5. Events 23.3.6. Interrupts 23.4. Register Summary - USARTn 23.5. Register Description 23.5.1. Receiver Data Register Low Byte 23.5.2. Receiver Data Register High Byte 23.5.3. Transmit Data Register Low Byte 23.5.4. Transmit Data Register High Byte 23.5.5. USART Status Register 23.5.6. Control A 23.5.7. Control B 23.5.8. Control C - Asynchronous Mode 23.5.9. Control C - Master SPI Mode 23.5.10. Baud Register 23.5.11. Control D 23.5.12. Debug Control Register 23.5.13. IrDA Control Register 23.5.14. IRCOM Transmitter Pulse Length Control Register 23.5.15. IRCOM Receiver Pulse Length Control Register 24. SPI - Serial Peripheral Interface 24.1. Features 24.2. Overview 24.2.1. Block Diagram 24.2.2. Signal Description 24.3. Functional Description 24.3.1. Initialization 24.3.2. Operation 24.3.2.1. Master Mode Operation 24.3.2.1.1. SS Pin Functionality in Master Mode - Multi-Master Support 24.3.2.1.2. Normal Mode 24.3.2.1.3. Buffer Mode 24.3.2.2. Slave Mode 24.3.2.2.1. SS Pin Functionality in Slave Mode 24.3.2.2.2. Normal Mode 24.3.2.2.3. Buffer Mode 24.3.2.3. Data Modes 24.3.2.4. Events 24.3.2.5. Interrupts 24.4. Register Summary - SPIn 24.5. Register Description 24.5.1. Control A 24.5.2. Control B 24.5.3. Interrupt Control 24.5.4. Interrupt Flags - Normal Mode 24.5.5. Interrupt Flags - Buffer Mode 24.5.6. Data 25. TWI - Two-Wire Interface 25.1. Features 25.2. Overview 25.2.1. Block Diagram 25.2.2. Signal Description 25.3. Functional Description 25.3.1. Initialization 25.3.2. General TWI Bus Concepts 25.3.2.1. Start and Stop Conditions 25.3.2.2. Bit Transfer 25.3.2.3. Address Packet 25.3.2.4. Data Packet 25.3.2.5. Transaction 25.3.2.6. Clock and Clock Stretching 25.3.2.7. Arbitration 25.3.2.8. Synchronization 25.3.3. TWI Bus State Logic 25.3.4. Operation 25.3.4.1. Electrical Characteristics 25.3.4.2. TWI Master Operation 25.3.4.2.1. Clock Generation 25.3.4.2.2. Transmitting Address Packets 25.3.4.2.2.1. Case M1: Arbitration Lost or Bus Error during Address Packet 25.3.4.2.2.2. Case M2: Address Packet Transmit Complete - Address not Acknowledged by Slave 25.3.4.2.2.3. Case M3: Address Packet Transmit Complete - Direction Bit Cleared 25.3.4.2.2.4. Case M4: Address Packet Transmit Complete - Direction Bit Set 25.3.4.2.3. Transmitting Data Packets 25.3.4.2.4. Receiving Data Packets 25.3.4.2.5. Quick Command Mode 25.3.4.3. TWI Slave Operation 25.3.4.3.1. Receiving Address Packets 25.3.4.3.1.1. Case S1: Address Packet Accepted - Direction Bit Set 25.3.4.3.1.2. Case S2: Address Packet Accepted - Direction Bit Cleared 25.3.4.3.1.3. Case S3: Collision 25.3.4.3.1.4. Case S4: STOP Condition Received 25.3.4.3.2. Receiving Data Packets 25.3.4.3.3. Transmitting Data Packets 25.3.4.4. Smart Mode 25.3.5. Interrupts 25.3.6. Sleep Mode Operation 25.4. Register Summary - TWIn 25.5. Register Description 25.5.1. Control A 25.5.2. Dual Mode Control Configuration 25.5.3. Debug Control 25.5.4. Master Control A 25.5.5. Master Control B 25.5.6. Master Status 25.5.7. Master Baud Rate 25.5.8. Master Address 25.5.9. Master DATA 25.5.10. Slave Control A 25.5.11. Slave Control B 25.5.12. Slave Status 25.5.13. Slave Address 25.5.14. Slave Data 25.5.15. Slave Address Mask 26. CRCSCAN - Cyclic Redundancy Check Memory Scan 26.1. Features 26.2. Overview 26.2.1. Block Diagram 26.3. Functional Description 26.3.1. Initialization 26.3.2. Operation 26.3.2.1. Checksum 26.3.3. Interrupts 26.3.4. Sleep Mode Operation 26.3.5. Debug Operation 26.4. Register Summary - CRCSCAN 26.5. Register Description 26.5.1. Control A 26.5.2. Control B 26.5.3. Status 27. CCL – Configurable Custom Logic 27.1. Features 27.2. Overview 27.2.1. Block Diagram 27.2.2. Signal Description 27.2.2.1. CCL Input Selection MUX 27.3. Functional Description 27.3.1. Basic Operation 27.3.1.1. Enable-Protected Configuration 27.3.1.2. Enabling, Disabling, and Resetting 27.3.1.3. Truth Table Logic 27.3.1.4. Truth Table Inputs Selection 27.3.1.5. Filter 27.3.1.6. Edge Detector 27.3.1.7. Sequencer Logic 27.3.1.8. Clock Source Settings 27.3.2. Interrupts 27.3.3. Events 27.3.4. Sleep Mode Operation 27.4. Register Summary - CCL 27.5. Register Description 27.5.1. Control A 27.5.2. Sequencer Control 0 27.5.3. Sequencer Control 1 27.5.4. Interrupt Control 0 27.5.5. Interrupt Flag 27.5.6. LUT n Control A 27.5.7. LUT n Control B 27.5.8. LUT n Control C 27.5.9. TRUTHn 28. AC – Analog Comparator 28.1. Features 28.2. Overview 28.2.1. Block Diagram 28.2.2. Signal Description 28.3. Functional Description 28.3.1. Initialization 28.3.2. Operation 28.3.2.1. Input Hysteresis 28.3.2.2. Input Sources 28.3.2.2.1. Pin Inputs 28.3.2.2.2. Internal Inputs 28.3.2.3. Power Modes 28.3.2.4. Signal Compare and Interrupt 28.3.3. Events 28.3.4. Interrupts 28.3.5. Sleep Mode Operation 28.4. Register Summary - AC 28.5. Register Description 28.5.1. Control A 28.5.2. Mux Control 28.5.3. DAC Voltage Reference 28.5.4. Interrupt Control 28.5.5. Status 29. ADC - Analog-to-Digital Converter 29.1. Features 29.2. Overview 29.2.1. Block Diagram 29.2.2. Signal Description 29.2.2.1. Definitions 29.3. Functional Description 29.3.1. Initialization 29.3.1.1. I/O Lines and Connections 29.3.2. Operation 29.3.2.1. Starting a Conversion 29.3.2.2. Clock Generation 29.3.2.3. Conversion Timing 29.3.2.4. Changing Channel or Reference Selection 29.3.2.4.1. ADC Input Channels 29.3.2.4.2. ADC Voltage Reference 29.3.2.4.3. Analog Input Circuitry 29.3.2.5. ADC Conversion Result 29.3.2.6. Temperature Measurement 29.3.2.7. Window Comparator Mode 29.3.3. Events 29.3.4. Interrupts 29.3.5. Sleep Mode Operation 29.4. Register Summary - ADCn 29.5. Register Description 29.5.1. Control A 29.5.2. Control B 29.5.3. Control C 29.5.4. Control D 29.5.5. Control E 29.5.6. Sample Control 29.5.7. MUXPOS 29.5.8. Command 29.5.9. Event Control 29.5.10. Interrupt Control 29.5.11. Interrupt Flags 29.5.12. Debug Run 29.5.13. Temporary 29.5.14. Result 29.5.15. Window Comparator Low Threshold 29.5.16. Window Comparator High Threshold 29.5.17. Calibration 30. UPDI - Unified Program and Debug Interface 30.1. Features 30.2. Overview 30.2.1. Block Diagram 30.2.2. Clocks 30.3. Functional Description 30.3.1. Principle of Operation 30.3.1.1. UPDI UART 30.3.1.2. BREAK Character 30.3.2. Operation 30.3.2.1. UPDI Enable 30.3.2.2. UPDI Disable 30.3.2.3. UPDI Communication Error Handling 30.3.2.4. Direction Change 30.3.3. UPDI Instruction Set 30.3.3.1. LDS - Load Data from Data Space Using Direct Addressing 30.3.3.2. STS - Store Data to Data Space Using Direct Addressing 30.3.3.3. LD - Load Data from Data Space Using Indirect Addressing 30.3.3.4. ST - Store Data from Data Space Using Indirect Addressing 30.3.3.5. LCDS - Load Data from Control and Status Register Space 30.3.3.6. STCS (Store Data to Control and Status Register Space) 30.3.3.7. REPEAT - Set Instruction Repeat Counter 30.3.3.8. KEY - Set Activation KEY 30.3.4. System Clock Measurement with UPDI 30.3.5. Interbyte Delay 30.3.6. System Information Block 30.3.7. Enabling of KEY Protected Interfaces 30.3.7.1. Chip Erase 30.3.7.2. NVM Programming 30.3.7.3. User Row Programming 30.3.8. Events 30.3.9. Sleep Mode Operation 30.4. Register Summary 30.5. Register Description 30.5.1. Status A 30.5.2. Status B 30.5.3. Control A 30.5.4. Control B 30.5.5. ASI Key Status 30.5.6. ASI Reset Request 30.5.7. ASI Control A 30.5.8. ASI System Control A 30.5.9. ASI System Status 30.5.10. ASI CRC Status 31. Instruction Set Summary 32. Electrical Characteristics 32.1. Disclaimer 32.2. Absolute Maximum Ratings 32.3. General Operating Ratings 32.4. Power Considerations 32.5. Power Consumption 32.6. Wake-Up Time 32.7. Peripherals Power Consumption 32.8. BOD and POR Characteristics 32.9. External Reset Characteristics 32.10. Oscillators and Clocks 32.11. I/O Pin Characteristics 32.12. USART 32.13. SPI 32.14. TWI 32.15. VREF 32.16. ADC 32.16.1. Internal Reference Characteristics 32.16.2. External Reference Characteristics 32.17. AC 32.18. UPDI 32.19. Programming Time 33. Typical Characteristics 33.1. Power Consumption 33.1.1. Supply Currents in Active Mode 33.1.2. Supply Currents in Idle Mode 33.1.3. Supply Currents in Power-Down Mode 33.1.4. Supply Currents in Standby Mode 33.1.5. Power-on Supply Currents 33.2. GPIO 33.3. VREF Characteristics 33.4. BOD Characteristics 33.5. ADC Characteristics 33.6. AC Characteristics 33.7. OSC20M Characteristics 33.8. OSCULP32K Characteristics 34. Ordering Information 35. Package Drawings 35.1. Online Package Drawings 35.2. 28-Pin SSOP 35.3. 32-Pin TQFP 35.4. 32-Pin VQFN 35.5. 48-Pin TQFP 35.6. 48-Pin UQFN 36. Data Sheet Revision History 36.1. Rev.A - 01/2020 36.2. Appendix - Obsolete Revision History 36.2.1. Obsolete Publication Rev.C - 08/2019 36.2.2. Obsolete Publication Rev.B - 03/2019 36.2.3. Obsolete Publication Rev.A - 02/2018 The Microchip Website Product Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Worldwide Sales and Service