PIR5
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLC4IF | CLC3IF | CLC2IF | CLC1IF | TMR5GIF | TMR3GIF | TMR1GIF | |
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 |
TMR5 Gate Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | TMR5 gate interrupt occurred (must be cleared in software) |
| 0 | No TMR5 gate occurred |
TMR3 Gate Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | TMR3 gate interrupt occurred (must be cleared in software) |
| 0 | No TMR3 gate occurred |
TMR1 Gate Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | TMR1 gate interrupt occurred (must be cleared in software) |
| 0 | No TMR1 gate occurred |
CLCx Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | A CLCx interrupt occurred |
| 0 | No CLCx interrupt occurred |