VREGCON

Note:
  1. 1.System and peripheral inputs should not exceed 500 kHz in ULP mode.

Voltage Regulator Control Register

Name:
VREGCON
Address:
0xEDA
Reset:
Access:
Bit76543210
PMSYS[1:0]VREGPM[1:0]
AccessROROR/WR/W
Resetgg10

Bits 5:4 – PMSYS[1:0]: System Power Mode Status bits

System Power Mode Status bits

ValueDescription
11 Reserved
10 ULP regulator is active
01 Main regulator in LP mode is active
00 Main regulator in HP mode is active

Bits 1:0 – VREGPM[1:0]: Voltage Regulator Power Mode Selection bit

Voltage Regulator Power Mode Selection bit

ValueDescription
11 Reserved. Do not use.
10 ULP regulator(1)
01 Main regulator in LP mode
00 Main regulator in HP mode