CLCxPOL
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POL | G4POL | G3POL | G2POL | G1POL | |||
| AccessR/W | R/W | R/W | R/W | R/W | |||
| Reset0 | x | x | x | x |
| Value | Description |
|---|---|
1 |
The output of the logic cell is inverted |
0 |
The output of the logic cell is not inverted |
| Value | Description |
|---|---|
1 |
The gate output is inverted when applied to the logic cell |
0 |
The output of the gate is not inverted |