High Byte Timer Counter Register - Split Mode
TCAn.HCNT contains the counter value in high byte timer. CPU and UPDI write access has priority over count, clear, or reload of the counter.
| Bit7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HCNT[7:0] | |||||||
| AccessR/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Reset0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Counter Value for High Byte Timer
These bits define the counter value in high byte timer.