LUT n Control A

Name:
LUTCTRLA
Offset:
0x05 + n*0x04 [n=0..1]
Reset:
0x00
Access:
Enable-Protected
Bit76543210
EDGEDETCLKSRCFILTSEL[1:0]OUTENENABLE
AccessR/WR/WR/WR/WR/WR/W
Reset000000

Bit 7 – EDGEDET: Edge Detection

Edge Detection

ValueDescription
0 Edge detector is disabled
1 Edge detector is enabled

Bit 6 – CLKSRC: Clock Source Selection

Clock Source Selection

This bit selects whether the peripheral clock (CLK_PER) or any input present on input line 2 (IN[2]) is used as clock (CLK_MUX_OUT) for an LUT.

The CLK_MUX_OUT of the even LUT is used for clocking the Sequential block of an LUT pair.

ValueDescription
0 CLK_PER is clocking the LUT
1 IN[2] is clocking the LUT

Bits 5:4 – FILTSEL[1:0]: Filter Selection

Filter Selection

These bits select the LUT output filter options:

ValueNameDescription
0x0 DISABLE Filter disabled
0x1 SYNCH Synchronizer enabled
0x2 FILTER Filter enabled
0x3 - Reserved

Bit 3 – OUTEN: Output Enable

Output Enable

This bit enables the LUT output to the LUTnOUT pin. When written to '1', the pin configuration of the PORT I/O Controller is overridden.
ValueDescription
0 Output to pin disabled
1 Output to pin enabled

Bit 0 – ENABLE: LUT Enable

LUT Enable

ValueDescription
0 The LUT is disabled
1 The LUT is enabled