Stop a DMA transfer occurring on the specified DMA Channel.
void dmac_channel_stop_transfer(
Dmac * p_dmac,
uint32_t ul_num)
Note: Under normal operation, the hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENAx register bit. The recommended way for software to disable a channel without losing data is to use the SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register.
Table 1. Parameters| Data direction |
Parameter name |
Description |
|---|
[in, out]
|
p_dmac
|
Module hardware register base address pointer
|
[in]
|
ul_num
|
DMA Channel number (range 0 to 3)
|