Supply Current (IDD)(1,2,4)

Table 1.
PIC18LF65/66K40 only
Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Device Characteristics	Min.	Typ.†	Max.	Units	Conditions
Param. No.	Sym.	Device Characteristics	Min.	Typ.†	Max.	Units	V_DD	Note
D100	I_{DD_XT4}	XT = 4 MHz	—	525	700	μA	3.0V
D100A	I_{DD_XT4}	XT = 4 MHz	—	325	—	μA	3.0V	PMD’s all `1`’s
D101	I_{DD_HFO16}	HFINTOSC = 16 MHz	—	2.1	3.0	mA	3.0V
D101A	I_{DD_HFO16}	HFINTOSC = 16 MHz	—	1.3	—	mA	3.0V	PMD’s all `1`’s
D102	I_{DD_HFOPLL}	HFINTOSC = 64 MHz	—	8.2	11	mA	3.0V
D102A	I_{DD_HFOPLL}	HFINTOSC = 64 MHz	—	4.8	—	mA	3.0V	PMD’s all `1`’s
D103	I_{DD_HSPLL64}	HS+PLL = 64 MHz	—	8.0	10	mA	3.0V
D103A	I_{DD_HSPLL64}	HS+PLL = 64 MHz	—	4.7	—	mA	3.0V	PMD’s all `1`’s
D104	I_{DD_IDLE}	IDLE mode, HFINTOSC = 16 MHz	—	1.4	—	mA	3.0V
D105	I_{DD_DOZE}⁽³⁾	DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16	—	1.5	—	mA	3.0V
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1.The test conditions for all I_DD measurements in active operation mode are: OSC1 = external square wave, from  rail-to-rail; all I/O pins are outputs driven low; MCLR = V_DD; WDT disabled. 2.The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3.I_{DD_DOZE} = [I_{DD_IDLE}(N-1)/N] + I_{DD_HFO}16/N where N = DOZE Ratio (see CPUDOZE* register). 4.PMD bits are all in the default state, no modules are disabled.
PIC18F65/66K40 only
Standard Operating Conditions (unless otherwise stated)
Param. No.	Sym.	Device Characteristics	Min.	Typ.†	Max.	Units	Conditions
Param. No.	Sym.	Device Characteristics	Min.	Typ.†	Max.	Units	V_DD	Note
D150	I_{DD_XT4}	XT = 4 MHz	—	575	750	μA	3.0V
D150A	I_{DD_XT4}	XT = 4 MHz	—	375	—	μA	3.0V	PMD’s all `1`’s
D151	I_{DD_HFO16}	HFINTOSC = 16 MHz	—	2.3	3.2	mA	3.0V
D151A	I_{DD_HFO16}	HFINTOSC = 16 MHz	—	1.4	—	mA	3.0V	PMD’s all `1`’s
D152	I_{DD_HFOPLL}	HFINTOSC = 64 MHz	—	8.5	12	mA	3.0V
D152A	I_{DD_HFOPLL}	HFINTOSC = 64 MHz	—	5.0	—	mA	3.0V	PMD’s all `1`’s
D153	I_{DD_HSPLL64}	HS+PLL = 64 MHz	—	8.3	11	mA	3.0V
D153A	I_{DD_HSPLL64}	HS+PLL = 64 MHz	—	4.8	—	mA	3.0V	PMD’s all `1`’s
D154	I_{DD_IDLE}	IDLE mode, HFINTOSC = 16 MHz	—	1.5	—	mA	3.0V
D155	I_{DD_DOZE}⁽³⁾	DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16	—	1.5	—	mA	3.0V
Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: 1.The test conditions for all I_DD measurements in active operation mode are: OSC1 = external square wave, from  rail-to-rail; all I/O pins are outputs driven low; MCLR = V_DD; WDT disabled. 2.The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3.I_{DD_DOZE} = [I_{DD_IDLE}(N-1)/N] + I_{DD_HFO}16/N where N = DOZE Ratio (see CPUDOZE* register). 4.PMD bits are all in the default state, no modules are disabled.