INTCON

Interrupt Control Register
Important: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
Name:
INTCON
Address:
0xFF2
Reset:
Access:
Bit76543210
GIE/GIEHPEIE/GIELIPENINT3EDGINT2EDGINT1EDGINT0EDG
AccessR/WR/WR/WR/WR/WR/WR/W
Reset0000111

Bit 7 – GIE/GIEH: Global Interrupt Enable bit

Global Interrupt Enable bit

ValueNameDescription
1 If IPEN = 1 Enables all unmasked interrupts and cleared by hardware for high-priority interrupts only
0 If IPEN = 1 Disables all interrupts
1 If IPEN = 0 Enables all unmasked interrupts and cleared by hardware for all interrupts
0 If IPEN = 0 Disables all interrupts

Bit 6 – PEIE/GIEL: Peripheral Interrupt Enable bit

Peripheral Interrupt Enable bit

ValueNameDescription
1 If IPEN = 1 Enables all low-priority interrupts and cleared by hardware for low-priority interrupts only
0 If IPEN = 1 Disables all low-priority interrupts
1 If IPEN = 0 Enables all unmasked peripheral interrupts
0 If IPEN = 0 Disables all peripheral interrupts

Bit 5 – IPEN: Interrupt Priority Enable bit

Interrupt Priority Enable bit

ValueDescription
1 Enable priority levels on interrupts
0 Disable priority levels on interrupts

Bits 0, 1, 2, 3 – INTxEDG: External Interrupt ‘x’ Edge Select bit

External Interrupt ‘x’ Edge Select bit

ValueDescription
1 Interrupt on rising edge of INTx pin
0 Interrupt on falling edge of INTx pin