ADCON2

ADC Control Register 2
Note:
  1. 1.To correctly calculate an average, the number of samples (set in ADRPT) must be 2ADCRS.
  2. 2.ADCRS = 'b111 is a reserved option.
  3. 3.This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions.
  4. 4.See Table 1 for Full mode descriptions.
Name:
ADCON2
Address:
0xF5A
Reset:
Access:
Bit76543210
ADPSISADCRS[2:0]ADACLRADMD[2:0]
AccessR/WR/WR/WR/WR/W/HCR/WR/WR/W
Reset00000000

Bit 7 – ADPSIS: ADC Previous Sample Input Select bits

ADC Previous Sample Input Select bits

ValueDescription
1 ADFLTR is transferred to ADPREV at start-of-conversion
0 ADRES is transferred to ADPREV at start-of-conversion

Bits 6:4 – ADCRS[2:0]: ADC Accumulated Calculation Right Shift Select bits

ADC Accumulated Calculation Right Shift Select bits

ValueNameDescription
0 to 7 ADMD = 'b100 Low-pass filter time constant is 2ADCRS, filter gain is 1:1
0 to 7 ADMD =' b011 to 'b001 The accumulated value is right-shifted by ADCRS (divided by 2ADCRS)(1,2)
x ADMD ='b000 to 'b001 These bits are ignored

Bit 3 – ADACLR: A/D Accumulator Clear Command bit(3)

A/D Accumulator Clear Command bit(3)

ValueDescription
1 ADACC, ADAOV and ADCNT registers are cleared
0 Clearing action is complete (or not started)

Bits 2:0 – ADMD[2:0]: ADC Operating Mode Selection bits(4)

ADC Operating Mode Selection bits(4)

ValueDescription
111-101 Reserved
100 Low-pass Filter mode
011 Burst Average mode
010 Average mode
001 Accumulate mode
000 Basic (Legacy) mode