TMRxCLK
Timer Clock Source Selection Register
Name:
TMRxCLK
Address:
0xFD2,0xFCC,0xFC6,0xF33
Reset:
Access:
Bit
7
6
5
4
3
2
1
0
CS[3:0]
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bits 3:0 – CS[3:0]: Timer Clock Source Selection bits
Timer Clock Source Selection bits
Refer to the clock source selection
table