CWGxSTR

CWG Steering Control Register (1)

Note:
  1. 1.The bits in this register apply only when MODE = '00x' (CWGxCON0, Steering modes).
  2. 2.This bit is double-buffered when MODE = '001'.
Name:
CWGxSTR
Address:
0x0F3E
Reset:
Access:
Bit76543210
OVRDOVRCOVRBOVRASTRDSTRCSTRBSTRA
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Reset00000000

Bits 4, 5, 6, 7 – OVRy: Steering Data OVR'y' bit

Steering Data OVR'y' bit

ValueNameDescription
x STRy = 1 CWGx'y' output has the CWG data input waveform with polarity control from POLy bit
1 STRy = 0 and POLy = x CWGx'y' output is high
0 STRy = 0 and POLy = x CWGx'y'output is low

Bits 0, 1, 2, 3 – STRy: STR'y' Steering Enable bit(2)

STR'y' Steering Enable bit(2)

ValueDescription
1 CWGx'y' output has the CWG data input waveform with polarity control from POLy bit
0 CWGx'y' output is assigned to value of OVRy bit