ADCON1

ADC Control Register 1
Name:
ADCON1
Address:
0xF59
Reset:
Access:
Bit76543210
ADPPOLADIPENADGPOLADDSEN
AccessR/WR/WR/WR/W
Reset0000

Bit 7 – ADPPOL: Precharge Polarity bit

Precharge Polarity bit

Action During 1st Precharge Stage
ValueNameDescription
x ADPRE=0 Bit has no effect
1 ADPRE>0 & ADC input is I/O pin Pin shorted to AVDD
0 ADPRE>0 & ADC input is I/O pin Pin shorted to VSS
1 ADPRE>0 & ADC input is internal CHOLD Shorted to AVDD
0 ADPRE>0 & ADC input is internal CHOLD Shorted to VSS

Bit 6 – ADIPEN: A/D Inverted Precharge Enable bit

A/D Inverted Precharge Enable bit

ValueNameDescription
x ADDSEN = 0 Bit has no effect
1 ADDSEN = 1 The precharge and guard signals in the second conversion cycle are the opposite polarity of the first cycle
0 ADDSEN = 1 Both Conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL

Bit 5 – ADGPOL: Guard Ring Polarity Selection bit

Guard Ring Polarity Selection bit

ValueDescription
1 ADC guard Ring outputs start as digital high during Precharge stage
0 ADC guard Ring outputs start as digital low during Precharge stage

Bit 0 – ADDSEN: Double-Sample Enable bit

Double-Sample Enable bit

ValueDescription
1 Two conversions are processed as a pair. The selected computation is performed after every second conversion.
0 Selected computation is performed after every conversion