ADCON0

ADC Control Register 0
Note:
  1. 1.This bit requires ON bit to be set.
  2. 2.If cleared by software while a conversion is in progress, the results of the conversion up to this point will be transferred to ADRES and the state machine will be reset, but the ADIF Interrupt Flag bit will not be set; filter and threshold operations will not be performed.
Name:
ADCON0
Address:
0x3F3
Reset:
Access:
Bit76543210
ONCONTCSFMGO
AccessR/WR/WR/WR/WR/W/HC/HS
Reset00000

Bit 7 – ON: ADC Enable

ADC Enable

ValueDescription
1 ADC is enabled
0 ADC is disabled

Bit 6 – CONT: ADC Continuous Operation Enable

ADC Continuous Operation Enable

ValueDescription
1 GO is retriggered upon completion of each conversion trigger until ADTIF is set (if SOI is set) or until GO is cleared (regardless of the value of SOI)
0 ADC is cleared upon completion of each conversion trigger

Bit 4 – CS: ADC Clock Selection

ADC Clock Selection

ValueDescription
1 Clock supplied from ADCRC dedicated oscillator
0 Clock supplied by FOSC, divided according to ADCLK register

Bit 2 – FM: ADC Results Format/Alignment Selection

ADC Results Format/Alignment Selection

ValueDescription
1 ADRES and ADPREV data are right justified
0 ADRES and ADPREV data are left justified, zero-filled

Bit 0 – GO: ADC Conversion Status(1,2)

ADC Conversion Status(1,2)

ValueDescription
1 ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the CONT bit
0 ADC conversion completed/not in progress