PIR3

Peripheral Interrupt Request Register 3
Note:
  1. 1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. 2.SPI1IF is a read-only bit. TO clear the interrupt condition, all bits in the SPI1INTF register must be cleared.
  3. 3.SPI1TXIF and SPI1RXIF are read-only bits and cannot be set/cleared by software.
Name:
PIR3
Address:
0x4B1
Reset:
Access:
Bit76543210
TMR0IFCCP1IFTMR1GIFTMR1IFTMR2IFSPI1IFSPI1TXIFSPI1RXIF
AccessR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSRRR
Reset00000000

Bit 7 – TMR0IF: TMR0 Interrupt Flag

TMR0 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 6 – CCP1IF: CCP1 Interrupt Flag

CCP1 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 5 – TMR1GIF: TMR1 Gate Interrupt Flag

TMR1 Gate Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 4 – TMR1IF: TMR1 Interrupt Flag

TMR1 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – TMR2IF: TMR2 Interrupt Flag

TMR2 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 2 – SPI1IF: SPI1 Interrupt Flag(2)

SPI1 Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – SPI1TXIF: SPI1 Transmit Interrupt Flag(3)

SPI1 Transmit Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – SPI1RXIF: SPI1 Receive Interrupt Flag(3)

SPI1 Receive Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred